Pattern contact opening to 2nd level poly si wordline

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Pattern contact opening to 2nd-level poly-Si (wordline), n+ source (bitline), and 1st level poly- Si (capacitor ground plane). Mask #4. The latter two are not shown in this cross-section. p p p -substrate (lightly doped) n+ SiO2 SiO2 CVD SiO2 SiO2 1st poly 2nd poly 8) Al deposition and metal patterning (Mask #5) p p p -substrate (lightly doped) n+ SiO2 SiO2 CVD SiO2 SiO2 1st poly 2nd poly thermal oxide Al Comments It is extremely difficult to pattern the narrow spacing (<30nm) using lithography because of alignment error and minimum resolution issues. This example use the controllable thermal oxididation process to fabricate this gap spacing.
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4 Problem 3 Process Description Cross Section along AB 1) Starting wafer, p- Si p -substrate (lightly doped) 2) Pad oxide growth Si 3 N 4 deposition Active area patterning (Mask #1) Channel stop Boron implantation Remove photoresist p -substrate (lightly doped) photoresist pad oxide Si3N4 Boron Channel Stop Implant 3) Local oxidation to grow field oxide Strip Si 3 N 4 Strip pad oxide (chemical dip) p p p -substrate (lightly doped) SiO2 SiO2 4) As implantation to form n + in active region Gate oxide oxidation p p p -substrate (lightly doped) n+ SiO2 SiO2 SiO2 5) Undoped poly-Si deposition Blanket As implant (low dose) to form n - poly-Si n- poly Si (lightly doped) p p p -substrate (lightly doped) n+ SiO2 SiO2 SiO2 As implant (low dose) 6) Masking resistor region with photoresist (Mask #2) As implantation (high dose) to form n + poly-Si n- poly Si (lightly doped) p p p -substrate (lightly doped) n+ SiO2 SiO2 n+ poly Si (heavily doped) SiO2 photoresist As implant (high dose) 7) Pattern poly-Si (Mask #3) Deposit CVD SiO 2 Diffuse and activate dopants in poly-Si with short time annealing ( 900°C) n- poly Si (lightly doped) p p p -substrate (lightly doped) n+ SiO2 SiO2 CVD SiO2
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  • Fall '04
  • ee142
  • SiO2, Silicon dioxide

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