Digital_Logic_Family_Lecturers.pdf

A phase splitter transistor controls which transistor

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A phase splitter transistor controls which transistor is active. Changes state faster than open-collector outputs. No external components are required. Advantages of Totem Pole Configuration:
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51 Totem pole Output Configuration of TTL Gates: NAND Circuit Diagram: k 7 . 4 k 1 A B Z Q1 Q2 Q3 +Vcc Q5 k 1 k 1 D1 Q4 Totem pole Output Configuration Z Q5 k 1 D1 Q4 +Vcc
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52 Open Collector Output Configuration of TTL Gates: NAND Circuit Diagram: Open collector Output Configuration Z k 7 . 4 k 1 A B Q1 Q2 Q3 +Vcc Q5 k 1
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53 Open Collector Output Configuration of TTL Gates: NAND A circuit that has LOW-state output circuitry, but no HIGH-state output circuitry. Requires an external pull-up resistor to enable the output to produce a HIGH-state. Open-Collector Outputs:
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54 Open Collector Output Configuration of TTL Gates NAND Allows the outputs of multiple gates to be directly connected. – – Called wired-AND . Can produce voltage levels in excess of 5 V. Can drive high-input current devices. Advantages of Open-Collector Outputs:
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55 Open Collector Output Configuration of TTL Gates NAND Open-Collector Applications:
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56 Tristate Output Configuration of TTL Gates Tristate output configuration : Three possible output states : Logic 1 state Logic 0 state, and High impedance state: controlled by an external ENABLE input ENABLE input: active or high impedance state. Active: logic ‘0’ and logic ‘1’. High impedance state: cut output state from state. Advantages: parallel connection of their inputs and outputs to a common bus line.
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57 Tristate Output Configuration of TTL Gates: Inverter Circuit Diagram: k 7 . 4 k 1 A Enable Z Q1 Q2 Q3 +Vcc Q5 k 1 k 1 D1 Q4 D2
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58 Tristate Output Configuration of TTL Gates: Inverter Circuit Diagram: k 7 . 4 k 1 A Enable Z Q1 Q2 Q3 +Vcc Q5 k 1 k 1 D1 Q4 D2 Enable A D2 Q1 Q2 Q3 Q4 D1 Q5 Z 1 0 RB/ OFF ON FA ON RA OFF ON FB OFF 1 1 1 RB/ OFF ON FA ON FA ON ON FB ON 0 0 0 FB/ ON ON FA ON FA OFF OFF RB OFF IND 0 1 FB/ ON ON FA ON FA OFF OFF RB OFF IND Operations/Truth Table: RB Reverse Bias FB Forward Bias IND Indetrmined
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59 TTL Subfamilies Transistor-Transistor Logic (TTL) Standard TTL Low power TTL High Speed TTL Shottky TTL Low power Schottky TTL
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60 Comparisons of TTL Subfamilies : Standard TTL: 1. Use of resistor value 2. Low power dissipation 3. Propagation delay depends largely on storage time and RC time constant Low power TTL: 1. Resistor value higher than that in standard TTL 2. Reduces power dissipation but increase propagation delay. High Speed TTL: 1. Low resistor values. 2. Reduces propagation delay. 3. Increase power dissipation.
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61 Schottky TTL: 1. Non saturating bipolar logic 2. Removes the storage time of transistors by preventing them from into saturation .
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  • Fall '17
  • Mr. Iqbal
  • Logic gate

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