Fundamentals-of-Microelectronics-Behzad-Razavi.pdf

V cc v ee 2 1 d d 2 out v q 3 q v b1 4 v in a b

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V CC V EE 2 1 D D 2 out V Q 3 Q V b1 4 V in (a) (b) Figure 13.15 (a) Push-pull stage with realization of current sources, (b) stage with input applied to base of . circuit can be reduced to that shown in Fig. 13.16(a), revealing a striking resemblance to a current Q 1 V CC 1 D Q 3 V b1 (b) Q 1 V CC Q 3 V b1 1 D (a) Figure 13.16 (a) Simplified diagram of a push-pull stage, (b) illustration of current mirror action. mirror. In fact, since (13.15) where the base current of is neglected and denotes the saturation current of , and since , we have (13.16) To establish a well-defined value for , diode is typically realized as a diode- connected bipolar transistor [Fig. 13.16(b)] in integrated circuits. Note a similar analysis can be applied to the bottom half of the circuit, namely, , , and . The second question can be answered with the aid of the simplified circuit shown in Fig. 13.17(a), where and represents the total small-signal resistance of and . Let us assume for simplicity that is relatively small and , further reducing the circuit to
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 697 (1) Sec. 13.4 Improved Push-Pull Stage 697 Q 1 Q R L 2 out Q 4 in (a) (b) v v r D 2 1 2 Q 1 Q R L 2 Q 4 in v N g m v π v π r π 1 1 1 v π r π 2 2 1 g π v R L out v v N (c) m2 out v 2 Figure 13.17 (a) Simplified circuit to calculate gain, (b) circuit with resistance of diodes neglected, (c) small-signal model. that illustrated in Fig. 13.17(b), where (13.17) Now, and operate as two emitter followers in parallel , i.e., as a single transistor having an equal to and a equal to [Fig. 13.17(c)]. For this circuit, we have and (13.18) It follows that (13.19) Multiplying the numerator and denominator by , dividing both by , and assuming , we obtain (13.20) a result expected of a follower transistor having a transconductance of . To compute , we must first derive the impedance seen at node , . From the circuit of Fig. 13.17(c), the reader can show that (13.21) It is important to note that this representation is valid for signals but not for biasing.
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 698 (1) 698 Chap. 13 Output Stages and Power Amplifiers (Note that for and , this expression reduces to the input impedance of a simple emitter follower.) Consequently, (13.22) (13.23) Example 13.9 Calculate the output impedance of the circuit shown in Fig. 13.18(a). For simplicity, assume Q 1 Q V CC V EE 2 1 D D 2 3 Q V b1 4 V in (a) (b) out R Q 1 Q 2 out R r O3 r O4 r D 2 Q 1 Q 2 out R r O4 r O3 (c) g m v π v π r π 1 2 π r 1 r O4 r O3 X i v X g + ( ) m2 (d) Q Figure 13.18 (a) Circuit for calculation of output impedance, (b) simplified diagram, (c) further simplifi- cation, (d) small-signal model. is small. Solution The circuit can be reduced to that in Fig. 13.18(b), and, with negligible, to that in Fig. 13.18(c). Utilizing the composite model illustrated in Fig. 13.17(c), we obtain the small-signal equivalent circuit of Fig. 13.18(d), where for and but not for and . Here, and act as a voltage divider: (13.24) A KCL at the output node gives (13.25)
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 699 (1) Sec. 13.5 Large-Signal Considerations 699 It follows that (13.26) (13.27) if .
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