ch07_solutions

# Plh t plh 2 203 ns 7 245 772 the worst case nmos path

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PLH + t PLH 2 = 2.03 ns

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7-245 7.72 The worst-case NMOS path contains 3 transistors (ABE or CBD). The worst-case PMOS path also contains 3 transistors t PHL = 10 - 12 2 3 25 x 10 - 6 ( 29 5 - 1 ( 29 ln 4 5 - 1 5 - 1  + 2 1 ( 29 5 - 1 = 19.3 ns t PLH = 10 - 12 2 3 10 x 10 - 6 ( 29 5 - 1 ( 29 ln 4 5 - 1 5 - 1  + 2 1 ( 29 5 - 1 = 48.3 ns | t P = t PLH + t PLH 2 = 33.8 ns 7.73 The worst-case NMOS path contains 3 transistors. t PHL = 10 - 12 2 3 25 x 10 - 6 ( 29 5 - 1 ( 29 ln 4 5 - 1 5 - 1  + 2 1 ( 29 5 - 1 = 19.3 ns 7.74 Student PSPICE will only accept 9 inverters. *PROBLEM 7.76(a) - NINE CASCADED INVERTERS VDD 1 0 DC 5 VIN 2 0 PULSE (0 5 0 0.1N 0.1N 20N 40N) * MN1 3 2 0 0 MOSN W=4U L=2U AS=16P AD=16P MP1 3 2 1 1 MOSP W=4U L=2U AS=16P AD=16P C1 3 0 200fF *AS=4UM*W - AD=4UM*W * MN2 4 3 0 0 MOSN W=4U L=2U AS=16P AD=16P MP2 4 3 1 1 MOSP W=4U L=2U AS=16P AD=16P C2 4 0 200fF * MN3 5 4 0 0 MOSN W=4U L=2U AS=16P AD=16P MP3 5 4 1 1 MOSP W=4U L=2U AS=16P AD=16P C3 5 0 200fF * MN4 6 5 0 0 MOSN W=4U L=2U AS=16P AD=16P MP4 6 5 1 1 MOSP W=4U L=2U AS=16P AD=16P C4 6 0 200fF * MN5 7 6 0 0 MOSN W=4U L=2U AS=16P AD=16P MP5 7 6 1 1 MOSP W=4U L=2U AS=16P AD=16P C5 7 0 200fF * MN6 8 7 0 0 MOSN W=4U L=2U AS=16P AD=16P MP6 8 7 1 1 MOSP W=4U L=2U AS=16P AD=16P C6 8 0 200fF * MN7 9 8 0 0 MOSN W=4U L=2U AS=16P AD=16P MP7 9 8 1 1 MOSP W=4U L=2U AS=16P AD=16P C7 9 0 200fF * MN8 10 9 0 0 MOSN W=4U L=2U AS=16P AD=16P MP8 10 9 1 1 MOSP W=4U L=2U AS=16P AD=16P
7-246 C8 10 0 200fF * MN9 11 10 0 0 MOSN W=4U L=2U AS=16P AD=16P MP9 11 10 1 1 MOSP W=4U L=2U AS=16P AD=16P C9 11 0 200fF * .OP .TRAN 0.025N 40N .MODEL MOSN NMOS KP=5E-5 VTO=0.91 GAMMA=0.99 +LAMBDA=.02 TOX=41.5N +CGSO=330P CGDO=330P CJ=3.9E-4 CJSW=510P .MODEL MOSP PMOS KP=2E-5 VTO=-0.77 GAMMA=0.5 +LAMBDA=.05 TOX=41.5N +CGSO=315P CGDO=315P CJ=2.0E-4 CJSW=180P .PROBE V(2) V(3) V(4) V(10) V(11) .END (a) 0s 10ns 20ns 30ns 40ns Time 6.0V 4.0V 2.0V 0V -2.0V v O v I (a) The minimum size inverters yield τ P = 1.75 ns. (b) The symmetrical inverters yield τ P = 1.25 ns. Note that these results are approximately two times the delay equation estimate because of the slope of the waveforms.

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7-247 7.75 (a) (b) A B CLK CLK V DD Z = A + B B A CLK CLK V DD Z = AB
7-248 7.76 (a) (b) A B CLK CLK V DD Z = A + B = AB A B CLK CLK V DD Z = A + B = AB 7.77 (a) (b) C A B CLK CLK V DD Z Z = A+B+C A B CLK CLK C V DD Z = ABC

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7-249 7.78 (a) (b) A B CLK CLK C V DD Z = A B C = A+B+C C A B CLK CLK V DD Z Z = A + B + C = ABC 7.79 Charge sharing occurs. Assuming C 2 and C 3 are discharged (the worst case) a ( 29 V B = C 1 V DD + C 2 0 ( 29 C 1 + C 2 = 2 C 2 V DD 2 C 2 + C 2 = 2 3 V DD | Node B drops to 2 3 V DD . b ( 29 V B = C 1 + C 2 ( 29 2 3 V DD + C 3 0 ( 29 C 1 + C 2 + C 3 = 3 C 2 2 3 V DD 2 C 2 + C 2 + C 2 = V DD 2 | Node B drops to 1 2 V DD . c ( 29 V B = C 1 V DD C 1 + C 2 + C 3 = RC 2 V DD RC 2 + C 2 + C 2 = R R + 2 V DD V IH R V DD - V IH ( 29 2V IH R 2V IH V DD - V IH = 2V IH NM H Using V DD = 5 V , V TN = 0.7 V , V TP = - 0.7 V in Eq. (8.9) : V IH = 5 5 ( 29 + 3 0.7 ( 29 + 5 - 0.7 ( 29 8 = 2.95 V | NM H = 3 5 ( 29 - 3 0.7 ( 29 - 5 - 0.7 ( 29 8 = 2.05 V R 2V IH NM H = 2 2.95 ( 29 2.05 = 2.88 | C 1 2.88C 2