Chapter 2: Routing Design Rules
Via Enclosure Rules
2-82
IC Compiler Technology File and Routing Rules Reference Manual
D-2010.03-SP2
IC Compiler Technology File and Routing Rules Reference Manual
Version D-2010.03-SP2
Figure 2-62
Fat Wire Via Enclosure Rule
Here is an example of the rule:
DesignRule {
layer1 = "Mx"
layer2 = "VIAx"
fatWireViaEncTblSize
= 4
fatWireViaEncWidthThresholdTbl
= (0.055, 0.060, 0.075, 0.170)
fatWireViaEncParallelLengthThresholdTbl = (0.12, 0.12, 0.14, 0.14)
fatWireViaEncMaxSpacingThresholdTbl
= (0.062, 0.068, 0.090, 0.134)
fatWireViaEnclosureTbl
= (0.008, 0.009, 0.012, 0.015)
fatWireViaArrayExcludedTbl
= (0, 0, 1, 0)
}
In this example, if the fat wire width W is greater than 0.055 but less than or equal to 0.060,
the parallel length L of the nearby metal is greater than or equal to 0.12, and the spacing S
to the nearby metal is less than 0.062, then the minimum enclosure E is 0.008. The last
attribute,
fatWireViaArrayExcludedTbl
, is set to 1 to waive the rule for a double via for the
corresponding set of values for W, L, S, and E.
S
n
E
n
W
n
L
n
