General Purpose Input Timing 132 Electrical Specifications Copyright 20072010

General purpose input timing 132 electrical

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Figure 6-11. General-Purpose Input Timing 132 Electrical Specifications Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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WAKE INT (A)(B) XCLKOUT Address/Data (internal) t d(WAKE-IDLE) t w(WAKE-INT) TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.9.4 Low-Power Mode Wakeup Timing Table 6-14 shows the timing requirements, Table 6-15 shows the switching characteristics, and Figure 6-12 shows the timing diagram for IDLE mode. Table 6-14. IDLE Mode Timing Requirements (1) MIN NOM MAX UNIT Without input qualifier 2t c(SCO) Pulse duration, external wake-up t w(WAKE-INT) cycles signal With input qualifier 5t c(SCO) + t w(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-13 . Table 6-15. IDLE Mode Switching Characteristics (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time, external wake signal to program execution resume (2) Wake-up from Flash Without input qualifier 20t c(SCO) cycles Flash module in active state With input qualifier 20t c(SCO) + t w(IQSW) t d(WAKE-IDLE) Wake-up from Flash Without input qualifier 1050t c(SCO) cycles Flash module in sleep state With input qualifier 1050t c(SCO) + t w(IQSW) Without input qualifier 20t c(SCO) cycles Wake-up from SARAM With input qualifier 20t c(SCO) + t w(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-13 . (2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up) signal involves additional latency. A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-12. IDLE Entry and Exit Timing Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 133 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 Table 6-16. STANDBY Mode Timing Requirements TEST CONDITIONS MIN NOM MAX UNIT Without input qualification 3t c(OSCCLK) Pulse duration, external t w(WAKE-INT) cycles wake-up signal With input qualification (1) (2 + QUALSTDBY) * t c(OSCCLK) (1) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-17. STANDBY Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time, IDLE instruction t d(IDLE-XCOL) 32t c(SCO) 45t c(SCO) cycles executed to XCLKOUT low Delay time, external wake t d(WAKE-STBY) signal to program execution cycles resume (1) Without input qualifier 100t c(SCO) Wake up from flash cycles Flash module in active With input qualifier 100t c(SCO) + t w(WAKE-INT) state Without input qualifier 1125t c(SCO) Wake up from flash cycles Flash module in sleep With input qualifier 1125t c(SCO) + t w(WAKE-INT) state Without input qualifier 100t c(SCO) cycles Wake up from SARAM With input qualifier 100t c(SCO) + t w(WAKE-INT) (1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
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