# 914 utilizes our knowledge of the output impedance to

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lemma illustrated in Fig. 9.14 utilizes our knowledge of the output impedance to quickly provide the voltage gain of the stage. CMOS Cascode Amplifier The foregoing analysis of the bipolar cascode amplifier can read- ily be extended to the CMOS counterpart. Depicted in Fig. 9.20(a) with an ideal current-source M M V b1 X in v I 1 out v M M X in v out v R R M 1 2 1 2 3 V b1 V b2 M V b2 4 V DD V DD (a) (b) op on Figure 9.20 (a) MOS cascode amplifier, (b) realization of load by a PMOS cascode. load, this stage also provides a short-circuit transconductance if . The output resistance is given by (9.22), yielding a voltage gain of (9.67) (9.68) (9.69) In other words, compared to a simple common-source stage, the voltage gain has risen by a factor of (the intrinsic gain of the cascode device). Since and are infinite for MOS devices (at low frequencies), we can also utilize (9.53) to arrive at (9.69). Note, however, that and

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 434 (1) 434 Chap. 9 Cascode Stages and Current Mirrors need not exhibit equal transconductances or output resistances (their widths and lengths need not be the same) even though they carry equal currents (why?). As with the bipolar counterpart, the MOS cascode amplifier must incorporate a cascode PMOS current source so as to maintain a high voltage gain. Illustrated in Fig. 9.20(b), the circuit exhibits the following output impedance components: (9.70) (9.71) The voltage gain is therefore equal to (9.72) Example 9.11 The cascode amplifier of Fig. 9.20(b) incorporates the following device parameters: , , mA. If , , and , determine the voltage gain. Solution With the particular choice of device parameters here, , , , and . We have (9.73) (9.74) and (9.75) Also, (9.76) (9.77) and (9.78) Equations (9.70) and (9.71) thus respectively give (9.79) (9.80) and (9.81) (9.82)
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 435 (1) Sec. 9.2 Current Mirrors 435 Exercise Explain why a lower bias current results in a higher output impedance in the above example. Calculate the output impedance for a drain current of 0.25 mA. 9.2 Current Mirrors 9.2.1 Initial Thoughts The biasing techniques studied for bipolar and MOS amplifiers in Chapters 4 and 6 prove inade- quate for high-performance microelectronic circuits. For example, the bias current of CE and CS stages is a function of the supply voltage—a serious issue because in practice, this voltage expe- riences some variation. The rechargeable battery in a cellphone or laptop computer, for example, gradually loses voltage as it is discharged, thereby mandating that the circuits operate properly across a range of supply voltages. Another critical issue in biasing relates to ambient temperature variations. A cellphone must maintain its performance at C in Finland and C in Saudi Arabia. To understand how temperature affects the biasing, consider the bipolar current source shown in Fig. 9.21(a), where Q 1 I 1 V BE R V CC R (a) (b) 2 1 I 1 V R V R 2 1 GS M 1 DD Figure 9.21 Impractical biasing of (a) bipolar and (b) MOS current sources.

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