# V dd m 1 m 2 out v in v 18 v figure 788 67 design the

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V DD M 1 M 2 out V in V = 1.8 V Figure 7.88 67. Design the common-gate stage depicted in Fig. 7.89 for an input impedance of 50 and a voltage gain of 5. Assume a power budget of 3 mW. V R DD D out V M 1 in V = 1.8 V I 1 Figure 7.89

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 371 (1) Sec. 7.6 Chapter Summary 371 68. Design the circuit of Fig. 7.90 such that operates 100 mV away from the triode region while providing a voltage gain of 4. Assume a power budget of 2 mW. V R DD D out V M 1 in V = 1.8 V R S Figure 7.90 69. Figure 7.91 shows a self-biased common-gate stage, where and serves as a V R DD D M 1 in V = 1.8 V R S C R V out G G Figure 7.91 low impedance so that the voltage gain is still given by . Design the circuit for a power budget of 5 mW and a voltage gain of 5. Assume so that the input impedance remains approximately equal to . 70. Design the CG stage shown in Fig. 7.92 such that it can accommodate an output swing of 500 V R DD D M 1 in V = 1.8 V R S V out R 2 R 1 Figure 7.92 m , i.e., can fall below its bias value by 250 mV without driving into the triode region. Assume a voltage gain of 4 and an input impedance of 50 . Select and . (Hint: since is biased 250 mV away from the triode region, we have .) 71. Design the source follower depicted in Fig. 7.93 for a voltage gain of 0.8 and a power budget of 2 mW. Assume the output dc level is equal to and the input impedance exceeds 10 k . 72. Consider the source follower shown in Fig. 7.94. The circuit must provide a voltage gain of
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 372 (1) 372 Chap. 7 CMOS Amplifiers M 1 V DD R G R S out V = 1.8 V in V Figure 7.93 M 1 V DD R G R S out V = 1.8 V in V X C 1 50 R L Figure 7.94 0.8 at 100 MHz while consuming 3 mW. Design the circuit such that the dc voltage at node is equal to . Assume the input impedance exceeds 20 k . 73. In the source follower of Fig. 7.95, serves as a current source. The circuit must operate M 1 V DD out V in V M 2 V b = 1.8 V Figure 7.95 with a power budget of 3 mW, a voltage gain of 0.9, and a minimum allowable output of 0.3 V (i.e., must remain in saturation if V). Assuming for both transistors, design the circuit. SPICE Problems In the following problems, use the MOS models and source/drain dimensions given in Ap- pendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and , respectively. 74. In the circuit of Fig. 7.96, is an ideal current source equal to 1 mA. M 1 V DD = 1.8 V out V I 1 10 k 1 k C 1 in V W L ( ( 1 Figure 7.96 (a) Using hand calculations, determine such that .

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 373 (1) Sec. 7.6 Chapter Summary 373 (b) Select for an impedance of ( ) at 50 MHz. (c) Simulate the circuit and obtain the voltage gain and output impedance at 50 MHz.. (d) What is the change in the gain if varies by ?
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