Figure 4 17 data access from program space address

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FIGURE 4-17: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 0 Program Counter 23 Bits Program Counter (1) TBLPAG 8 Bits EA 16 Bits Byte Select 0 1/0 User/Configuration Table Operations (2) Space Select 24 Bits 1/0 Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘ 0 ’ to maintain word alignment of data in the Program and Data Spaces. 2: Table operations are not required to be word-aligned. Table Read operations are permitted in the configura- tion memory space.
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2013-2016 Microchip Technology Inc. DS70005144E-page 81 dsPIC33EVXXXGM00X/10X FAMILY 4.7.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the Program Space without going through the Data Space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a Program Space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to Data Space addresses. Program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. The TBLRDL and TBLWTL instructions access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from Program Space. Both function as either byte or word operations. TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the Program Space location (P<15:0>) to a data address (D<15:0>). - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘ 1 ’; the lower byte is selected when it is ‘ 0 ’. TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. The ‘phantom’ byte (D<15:8>) is always ‘ 0 ’. - In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, as in the TBLRDL instruction. The data is always ‘ 0 ’ when the upper ‘phantom’ byte is selected (Byte Select = 1 ). Similarly, two table instructions, TBLWTH and TBLWTL , are used to write individual bytes or words to a Program Space address. The details of their operation are explained in Section 5.0 “Flash Program Memory” . For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user application and configuration spaces. When TBLPAG<7> = 0 , the table page is located in the user memory space. When TBLPAG<7> = 1 , the page is located in configuration space. Accessing the program memory with table instructions is shown in Figure 4-18 .
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