popback 2354 data 1 data qint popfront 354 data 2 while qint size 0 checking

Popback 2354 data 1 data qint popfront 354 data 2

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data = q_int.pop_back(); // {2,3,5,4} data = 1data = q_int.pop_front(); // {3,5,4} data = 2while (q_int.size()> 0) // checking queue sizedata = q_int.pop_back(); // loop executes 3 timesq_bit.push_front(8’h01); // {’h01}q_bit.push_back(8’h45); // {’h01,’h45}q_bit.push_front(8’h89); // {’89,’h01,’h45}endQueue methods support inserting and extracting elements. This example illustrates use of several of the methods.Pause here and examine this example using queue methods.
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SystemVerilog Language and Application193193SystemVerilog for Verification7/31/07Queue Indexing Exampleint q_int[$]; // queue declaration syntaxbit [7:0] q_bit[$:100]; // queue with maximum size of 100initial beginq_int = {0,q_int}; // {0}q_int = {q_int,1}; // {0,1}q_int = {2,q_int}; // {2,0,1}q_int = {q_int[0],3,q_int[1:$]}; // {2,3,0,1}q_int = {q_int[0:2],4,q_int[3]}; // {2,3,0,4,1}q_int = {q_int[0:1],q_int[3:4]}; // {2,3,4,1}q_int = {q_int[0:1],5,q_int[2:3]}; // {2,3,5,4,1}data = q_int[$]; q_int = q_int[0:$-1]; // {2,3,5,4} data = 1data = q_int[0]; q_int = q_int[1:$]; // {3,5,4} data = 2while (q_int.size()> 0) begin // checking queue sizedata = q_int[$]; // loop executes 3 timesq_int = q_int[0:$-1]; endq_bit = {8’h01,q_bit}; // {’h01}q_bit = {q_bit,8’h45}; // {’h01,’h45}q_bit = {8’h89,q_bit}; // {’89,’h01,’h45}endA queue is an array, so if you really want to, you can still use array indexing to insert and extract elements. As this example illustrates, you probably don’t really want to. The queue methods are much more friendly.We won’t bother examining this slide too closely.
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SystemVerilog Language and Application195195SystemVerilog for Verification7/31/07QuizMatch the array that best meets each design need: A.Packed arrayB.Unpacked arrayC.Dynamic arrayD.Associative arrayE. Queue1.I want to concisely code an RTL instruction processor to strip the opcode, address and data fields off the instruction word…2.I need to validate the architecture of my processor stack…3.I need to validate the architecture of my packet data temporary storage…4.I need to validate the architecture of my instruction cache…5.I want to perform matrix operations on fixed-size “chunks” of data of the real type…Solutions in Appendix A
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SystemVerilog Language and Application71July 31, 2007User-Defined Data Types and StructuresChapter 5
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SystemVerilog Language and Application737/31/0773SystemVerilog for DesignPrimitive and User-Defined TypesPrimitive data typesBuilt-in types not constructed from other data typese.g.bit,logic,int,realUser-defined data typesTypes named withtypedefTypes constructed from other typese.g. vectors and arraysC-likeenumfor user-defined values setsC-likestructto bundle multiple variables into one objectC-likeunionto store different data types in the same spaceSupport:union?A primitive data-type is a built-in type that is not constructed from other types. Any other datatype is user-defined. This includes types that you named with the typedef keyword and types you construct from other types, such arrays, enumerations, structures and unions.
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SystemVerilog Language and Application747/31/0774SystemVerilog for DesignType DefinitionYou can declare and name a typeusingtypedefVerilog standard typesSystemVerilog user-defined typesYou can use your type nameanywhere you can use a typee.g. variable or port declaration
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