72 flynns bottleneck if one can bypass n branches

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If bounded to single basic block, speedup is 1.72 (Flynn’s bottleneck) If one can bypass n branches (hypothetically), then: Branches Bypassed 0 1 2 8 32 128 Speedup 1.72 2.72 3.62 7.21 14.8 24.4 51.2
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© 2005 Mikko Lipasti 17 Speculative Execution Riseman & Foster showed potential But no idea how to reap benefit 1979: Jim Smith patents branch prediction at Control Data Predict current branch based on past history Today: virtually all processors use branch prediction
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© 2005 Mikko Lipasti 18 Instruction Flow in Context I-cache FETCH DECODE COMMIT D-cache Branch Predictor Instruction Buffer Store Queue Reorder Buffer Integer Floating-point Media Memory Instruction Register Data Memory Data Flow EXECUTE (ROB) Flow Flow
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© 2005 Mikko Lipasti 19 Improving I-Cache Performance Larger cache size Code compression Instruction registers Increased associativity Conflict misses less of a problem than in data caches Larger line size Spatial locality inherent in sequential program I-stream Code layout Maximize instruction stream’s spatial locality Cache prefetching Next-line, streaming buffer Branch target (even if not taken) Other types of I-cache organization Trace cache [Ch. 9]
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Recap Branch types Control dependences Improving instruction cache performance
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  • Fall '09
  • PROFGURISOHI
  • Central processing unit, CPU cache, Branch predictor, branch, Instruction Flow, addi addi addi

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