Table 6 36 Relationship Between Parameters Configured in XTIMING and Duration

Table 6 36 relationship between parameters configured

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Table 6-36. Relationship Between Parameters Configured in XTIMING and Duration of Pulse DURATION (ns) (1) (2) DESCRIPTION X2TIMING = 0 X2TIMING = 1 LR Lead period, read access XRDLEAD × t c(XTIM) (XRDLEAD × 2) × t c(XTIM) AR Active period, read access (XRDACTIVE + WS + 1) × t c(XTIM) (XRDACTIVE × 2 + WS + 1) × t c(XTIM) TR Trail period, read access XRDTRAIL × t c(XTIM) (XRDTRAIL × 2) × t c(XTIM) LW Lead period, write access XWRLEAD × t c(XTIM) (XWRLEAD × 2) × t c(XTIM) AW Active period, write access (XWRACTIVE + WS + 1) × t c(XTIM) (XWRACTIVE × 2 + WS + 1) × t c(XTIM) TW Trail period, write access XWRTRAIL × t c(XTIM) (XWRTRAIL × 2) × t c(XTIM) (1) t c(XTIM) Cycle time, XTIMCLK (2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0), then WS = 0. Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal device hardware is included to detect illegal settings. 6.14.1 USEREADY = 0 If the XREADY signal is ignored (USEREADY = 0), then: Lead: LR t c(XTIM) LW t c(XTIM) These requirements result in the following XTIMING register configuration restrictions: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 1 0 0 1 0 0 0, 1 Examples of valid and invalid timing when not sampling XREADY: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid (1) 0 0 0 0 0 0 0, 1 Valid 1 0 0 1 0 0 0, 1 (1) No hardware to detect illegal XTIMING configurations Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 149 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then: 1 Lead: LR t c(XTIM) LW t c(XTIM) 2 Active: AR 2 × t c(XTIM) AW 2 × t c(XTIM) NOTE Restriction does not include external hardware wait states. These requirements result in the following XTIMING register configuration restrictions : XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 1 1 0 1 1 0 0, 1 Examples of valid and invalid timing when using synchronous XREADY: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid (1) 0 0 0 0 0 0 0, 1 Invalid (1) 1 0 0 1 0 0 0, 1 Valid 1 1 0 1 1 0 0, 1 (1) No hardware to detect illegal XTIMING configurations 150 Electrical Specifications Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then: 1 Lead: LR t c(XTIM) LW t c(XTIM) 2 Active: AR 2 × t c(XTIM) AW 2 × t c(XTIM) 3 Lead + Active: LR + AR 4 × t c(XTIM) LW + AW 4 × t c(XTIM) NOTE Restrictions do not include external hardware wait states.
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