Reserved0101Reserved (meaning in PCI-X)0110Memory Read0111MemorWriteMemory Write1000Reserved (meaning in PCI-X)1001Reserved (meaning in PCI-X)1010CfitiRdConfiguration Read1011Configuration Write1100Memory Read Multiple1101Dual Address Cycle1110Memory Read Line1111Memory Write and Invalidate
Read TransactionDEVSEL# must be asserted by target within 1 to 3 cycles after address phaseTRDY# must be asserted by target within 16 cycles after address phase
Read Transaction Details
PCI ArbitrationDetails of arbitration policy notspecifiedFactors in priority and devicelatency timerHiddbiidlHidden arbitration reduces latencyLocated in PC Chipset (e.g. Southbridge)
Basic ArbitrationDevice a has bus (and continues to assert REQ because it anticipates wanting to do further transactions)Device b requests busCoincidentally, device a is through with the first of its transactions
Write Transaction Details
Termination by Target•Retry --STOP# is asserted before target ever asserts TRDY# (before any data is transmitted). Typically because target is unable to present anyTypically because target is unable to present any data within the allowed time period (16 cycles)• Disconnect -- STOP# is asserted by the targetDisconnect STOP# is asserted by the target during or after first data phase. Master will repeat the transaction but with modified start address•Target Abort – STOP# is asserted simultaneously with deactivation of DEVSEL#. Typically an unrecoverable errorunrecoverable error.
Delayed Transactions•Retry terminations result in “delayed transactions”•Typically used by slower devices •The target terminates the transaction with the initiator but continues to internally process the request, storing the results in a buffer•When the initiator retries the transaction, the target provides the requested data
PCI ConfigurationDuring configuration…Enumeration determines PCI devices and functions connected, and their key characteristics, including amount of address space they require.Each device (capable of being a bus master) also reports its maximum permissible bus access grant delay (Max_Lat) and the minimum time it must have control over the bus (Min_Gnt).