Reserved 0101 Reserved meaning in PCI X 0110 Memory Read 0111 Memor Write

Reserved 0101 reserved meaning in pci x 0110 memory

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Reserved 0101 Reserved (meaning in PCI-X) 0110 Memory Read 0111 Memor Write Memory Write 1000 Reserved (meaning in PCI-X) 1001 Reserved (meaning in PCI-X) 1010 C fi ti R d Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate
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Read Transaction DEVSEL# must be asserted by target within 1 to 3 cycles after address phase TRDY# must be asserted by target within 16 cycles after address phase
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Read Transaction Details
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PCI Arbitration Details of arbitration policy not specified Factors in priority and device latency timer Hidd bi i d l Hidden arbitration reduces latency Located in PC Chipset (e.g. Southbridge)
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Basic Arbitration Device a has bus (and continues to assert REQ because it anticipates wanting to do further transactions) Device b requests bus Coincidentally, device a is through with the first of its transactions
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Write Transaction
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Write Transaction Details
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Termination by Target Retry -- STOP# is asserted before target ever asserts TRDY# (before any data is transmitted). Typically because target is unable to present any Typically because target is unable to present any data within the allowed time period (16 cycles) • Disconnect -- STOP# is asserted by the target Disconnect STOP# is asserted by the target during or after first data phase. Master will repeat the transaction but with modified start address Target Abort – STOP# is asserted simultaneously with deactivation of DEVSEL#. Typically an unrecoverable error unrecoverable error.
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Delayed Transactions Retry terminations result in “delayed transactions” Typically used by slower devices The target terminates the transaction with the initiator but continues to internally process the request, storing the results in a buffer When the initiator retries the transaction, the target provides the requested data
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PCI Configuration During configuration… Enumeration determines PCI devices and functions connected, and their key characteristics, including amount of address space they require. Each device (capable of being a bus master) also reports its maximum permissible bus access grant delay (Max_Lat) and the minimum time it must have control over the bus (Min_Gnt).
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