Tblwtl msb using tblrdh tblwth 0x0000 tblpag 0x7f

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TBLWTL , MSB Using TBLRDH / TBLWTH 0x0000 (TBLPAG = 0x7F) 0xFFFF lsw Using TBLRDL / TBLWTL , MSB Using TBLRDH / TBLWTH (Instruction & Data) No Writes Allowed No Writes Allowed No Writes Allowed No Writes Allowed RAM 0x7FFF 0x8000
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2013-2016 Microchip Technology Inc. DS70005144E-page 71 dsPIC33EVXXXGM00X/10X FAMILY Allocating different Page registers for read and write access allows the architecture to support data movement between different pages in the data memory. This is accomplished by setting the DSRPAG register value to the page from which you want to read, and configure the DSWPAG register to the page to which it needs to be written. Data can also be moved from different PSV to EDS pages by configuring the DSRPAG and DSWPAG registers to address PSV and EDS space, respectively. The data can be moved between pages by a single instruction. When an EDS or PSV page overflow or underflow occurs, EA<15> is cleared as a result of the register indirect EA calculation. An overflow or underflow of the EA in the EDS or PSV pages can occur at the page boundaries when: The initial address, prior to modification, addresses an EDS or a PSV page. The EA calculation uses Pre- or Post-Modified Register Indirect Addressing. However, this does not include Register Offset Addressing. In general, when an overflow is detected, the DSxPAG register is incremented and the EA<15> bit is set to keep the base address within the EDS or PSV window. When an underflow is detected, the DSxPAG register is decremented and the EA<15> bit is set to keep the base address within the EDS or PSV window. This creates a linear EDS and PSV address space, but only when using the Register Indirect Addressing modes. Exceptions to the operation described above arise when entering and exiting the boundaries of Page 0, EDS and PSV spaces. Table 4-43 lists the effects of overflow and underflow scenarios at different boundaries. In the following cases, when an overflow or underflow occurs, the EA<15> bit is set and the DSxPAG is not modified; therefore, the EA will wrap to the beginning of the current page: Register Indirect with Register Offset Addressing Modulo Addressing Bit-Reversed Addressing TABLE 4-43: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS AND PSV SPACE BOUNDARIES ( 2 , 3 , 4 ) O/U, R/W Operation Before After DSxPAG DS EA<15> Page Description DSxPAG DS EA<15> Page Description O, Read [++Wn] or [Wn++] DSRPAG = 0x1FF 1 EDS: Last Page DSRPAG = 0x1FF 0 See Note 1 O, Read DSRPAG = 0x2FF 1 PSV: Last lsw Page DSRPAG = 0x300 1 PSV: First MSB Page O, Read DSRPAG = 0x3FF 1 PSV: Last MSB Page DSRPAG = 0x3FF 0 See Note 1 O, Write DSWPAG = 0x1FF 1 EDS: Last Page DSWPAG = 0x1FF 0 See Note 1 U, Read [--Wn] or [Wn--] DSRPAG = 0x001 1 PSV Page DSRPAG = 0x001 0 See Note 1 U, Read DSRPAG = 0x200 1 PSV: First lsw Page DSRPAG = 0x200 0 See Note 1 U, Read DSRPAG = 0x300 1 PSV: First MSB Page DSRPAG = 0x2FF 1 PSV: Last lsw Page Legend: O = Overflow, U = Underflow, R = Read, W = Write Note 1: The Register Indirect Addressing now addresses a location in the Base Data Space (0x0000-0x8000).
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