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the alternative uses one transistor for control and one capacitor to store a single bit •theword line selects which row of memory cells will be active and connects the capacitor to the input/ output line (i.e. the bit line) •the bit line either stores a charge on the capacitor (write) or sense the charge on the capacitor (read) CS251 Winter 2016 127 Digital Design
Sequential Circuits Dynamic RAM (DRAM) •to write (store a bit) -activate word line -put value on bit line -it charges or discharges capacitor (like charging or discharging a small battery) •to read a bit -problem: capacitor only stores a tiny amount of charge -put ½ VDDon the bit line -when the capacitor is connected (i.e. word line = 1) the voltage on the bit line will increase slightly (if the capacitor is storing a 1) or decrease slightly (if storing a 0) -that change is amplified to a proper 0 or 1 voltage level CS251 Winter 2016 128 Digital Design
Sequential Circuits Two-level Decoding •for a realistically sized memory, say 4M, the decoder would have 22 address lines and roughly 4 million word select lines (i.e. a huge decoder) •Key Idea:have a much bigger column size, i.e. -4 million rows x 1 column stores the same amount of information as 2,000 rows x 2,000 columns. -called two-level decoding i.e. you need to specify the row and the column where the bit is stored •use a decoder that can takes an 11 bit address and selects which one of 2K different word lines to make active •then use a multiplexor that takes an 11 bit address and selects which of the 2K columns you actually want CS251 Winter 2016 129 Digital Design
Sequential Circuits CS251 Winter 2016 130 Digital Design Two-level Decoding •address is split into 2 halves •read in upper half of addr •use to select the row •read in lower half •use to select the column •interpret 22 bit address as -11 bit row address followed by -11 bit column address -e.g. rrrrrrrrrrr ccccccccccc
Sequential Circuits Dynamic RAM (DRAM) •capacitors only store a charge for a short amount of time, i.e. on the order of milliseconds •must refresh the charge on the capacitor, i.e. sense if it is a 0 or a 1 and rewrite that value •refresh happens one row at a time •typical values -refresh every 4 ms -refresh takes 80 ns -fraction of time dedicated to refreshing 4% -i.e. memory not available 4% of the time, i.e. processor must wait CS251 Winter 2016 131 Digital Design
Sequential Circuits Dynamic RAM (DRAM) •DRAM is cheaper per bit than SRAM, but slower •refresh controller must also allow read/write access •there is the possibility of getting more bits out at a time (e.g. page-mode RAM) •SDRAM(synchronized DRAM) uses external clock to synchronize with processor What is Used Where? •use a register file for registers •use SRAM for the processor’s memory cache (L1, L2, L3)•use SDRAM for main memory •called amemory hierarchy, more on this and caching later…CS251 Winter 2016 132 Digital Design
Finite-State Machines (FSM) Overview a FSM consists of two circuits 1.