Table 39 GPIO Control Registers Name 1 Address Size x16 Register Description

Table 39 gpio control registers name 1 address size

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Table 39. GPIO Control Registers Name (1) Address Size (x16) Register Description Bit Description GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0-GPIO31) Figure 53 GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0-GPIO15) Figure 55 GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16-GPIO31) Figure 56 GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0-GPIO15) Figure 47 GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16-GPIO31) Figure 48 GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0-GPIO31) Figure 59 GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0-GPIO31) Figure 62 GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32-GPIO63) Figure 54 GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32-GPIO47) Figure 57 GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register (GPIO48 - GPIO63) Figure 58 GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32-GPIO47) Figure 49 GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48-GPIO63) Figure 50 GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32-GPIO63) Figure 60 GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32-GPIO63) Figure 63 GPCMUX1 0x6FA6 2 GPIO C MUX 1 Register (GPIO64-GPIO79) Figure 51 GPCMUX2 0x6FA8 2 GPIO C MUX 2 Register (GPIO80-GPIO87) Figure 52 GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64-GPIO87) Figure 61 GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64-GPIO87) Figure 64 (1) The registers in this table are EALLOW protected. See Section 7.2 for more information. Table 40. GPIO Interrupt and Low Power Mode Select Registers Size Name (1) Address Register Description Bit Description (x16) GPIOXINT1SEL 0x6FE0 1 XINT1 Source Select Register (GPIO0-GPIO31) Figure 71 GPIOXINT2SEL 0x6FE1 1 XINT2 Source Select Register (GPIO0-GPIO31) Figure 71 GPIOXNMISEL 0x6FE2 1 XNMI Source Select Register (GPIO0-GPIO31) Figure 71 GPIOXINT3SEL 0x6FE3 1 XINT3 Source Select Register (GPIO32 - GPIO63) Table 82 GPIOXINT4SEL 0x6FE4 1 XINT4 Source Select Register (GPIO32 - GPIO63) Table 82 GPIOXINT5SEL 0x6FE5 1 XINT5 Source Select Register (GPIO32 - GPIO63) Table 82 GPIOXINT6SEL 0x6FE6 1 XINT6 Source Select Register (GPIO32 - GPIO63) Table 82 GPIOXINT7SEL 0x6FE7 1 XINT7 Source Select Register (GPIO32 - GPIO63) Table 82 GPIOLPMSEL 0x6FE8 1 LPM wakeup Source Select Register (GPIO0-GPIO31) Figure 72 (1) The registers in this table are EALLOW protected. See Section 7.2 for more information. 66 Flash and OTP Memory Blocks SPRUFB0D–September 2007–Revised March 2010 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
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General-Purpose Input/Output (GPIO) To plan configuration of the GPIO module, consider the following steps: Step 1. Plan the device pin-out: Through a pin multiplexing scheme, a lot of flexibility is provided for assigning functionality to the GPIO-capable pins. Before getting started, look at the peripheral options available for each pin, and plan pin-out for your specific system. Will the pin be used as a general purpose input or output (GPIO) or as one of up to three available peripheral functions? Knowing this information will help determine how to further configure the pin.
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