E 4 pts the pa 8500 was derived from the pa 8000

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e. [4 pts] The PA-8500 was derived from the PA-8000, which had no on-chip caches (at the time, HP’s proprietary process technology did not effectively support large amounts of on-chip SRAM; the PA-8500 was fabbed by Intel, so it did not have this limitation). Architecturally, the PA-8000 was similar in that it had a single level of cache, implemented using off-chip SRAM. Why do you think HP designers continued the unconventional single-level approach, even when they had access to on-chip SRAM for the PA-8500? Do you think this was the right decision? Justify your answer. Adding 2 nd level is a fairly significant ripup of the existing design, particularly in a cache-coherent multiprocessor (protocols for multilevel caches can get quite involved). Given that HP was moving away from PA-RISC and wanted to minimize its investment and risk, this was probably the right business decision, though arguably not the right technical decision.
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ECE/CS 752 Spring 2008 Midterm 2 -- Page 10 5. Out-of-order Scheduling Replay [20 pts] Given the following code, assume that array A begins at address 0x0, and array B is placed consecutively after A in memory, and that each “double” array entry consumes 8 bytes (64 bits). The data cache is initially empty. double A[1024], B[1024]; for(int i=0; i<1000; i++) { A[i] = 35.0 * B[i]; } The corresponding machine/assembly code for the loop body looks like this: loop: addi r1,r1,1 // increment i cmp r1,#1000 // compare to 1000 bge done // exit loop if done load f1,0(r2) // r2 points to B[i] fmul f2,f1,f4 // f4 preloaded with 35.0 store f2,0(r4) // r4 points to A[i] addi r2,r2,8 addi r4,r4,8 jump loop done: … You are to analyze the behavior of a 2-wide speculative scheduler in terms of the number of unnecessarily executed instructions under varying scheduling recovery models, as described in the Kim reading (“Understanding Scheduling Replay Schemes”). Assume the following: The same 4-stage pipeline from schedule to execute shown in Fig. 5 of [Kim]. Cache misses are detected at the end of this pipeline, so there are up to 4x2=8 instructions in flight before the scheduler finds out that a cache miss occurred. Load instructions have 1-cycle latency (that is, they execute in the 4 th stage from issue) Integer, branch, and store-address have a 1-cycle latency The floating-point multiply (fmul) instructions have 3-cycle latency that extends beyond the 1 EX cycle shown in the paper All execution units are fully pipelined There are two of each type of functional unit, so any instruction pair can issue in each cycle Stores are split into two micro-ops: a store-address micro-op, which issues speculatively as soon as its address-source register is ready, and the store-data microp, which never issues speculatively, but executes at commit Loads issue speculatively, even if prior store addresses have not yet issued The select logic will always issue the oldest of the ready instructions Perfect branch prediction and an infinitely large issue queue and reorder buffer, so there are always more instructions to issue (from future iterations of the loop) 128-byte cache lines, leading to a 6.25% steady-state miss rate for loads from B[] (1 load in 16 will miss).
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