all the input combinations. For each input combination check to see if the output is connected to either Gnd (enter 0 as the output) or Vdd (enter 1 as the output). Once you have completed all the inputs you will have the truth table of your logic gate. If there cases where the output isn’t driven, or both paths are on at the same time, it is not a valid gate. Problem 4.4 When is the output a logical 1? Determine whether the switch should be connected or disconnected to set the output to logical 1.
4.5. BUILDING CMOS LOGIC GATES 105 Problem 4.5 When is the output a logical 0? For each of the following two circuits, determine when the output is a logical 0. Choose one of the following options: A. When A is connected. B. When B is connected. C. When A and B are connected. D. When A or B is connected. E. When neither are connected.
106 CHAPTER 4. INTRODUCTION TO DIGITAL LOGIC Problem 4.6 Which are valid logic gates? By using the rules described above, determine which of the following three CMOS circuits are valid logic gates. Problem 4.7 More practice: Is the following a valid logic gate? 4.5.1 How to create a logic gate? It is not that complicated as long as you follow a few simple rules. First notice that nMOS transistors connect the output to Gnd and turn on when the inputs are HIGH, and pMOS transistors connect the output to Vdd when their input is LOW. This means that 1 inputs can only cause the output to be 0, and 0 inputs can only cause the output to be 1. Said a different way, all MOS gates will invert. They can only make inverters, or NAND gates or NOR gates. To make an AND gate, you need to make a NAND gate and then add an inverter to its output! When building a logic circuit, its helpful to ask two questions: What conditions should cause
4.5. BUILDING CMOS LOGIC GATES 107 the output to be 0? We use the answer to this question to create the nMOS transistor circuit that connect the output to Gnd. If two inputs both must be true for the output to low, then we need to create a circuit that only connects the output to Gnd when both transistors are on. This condition occurs when the two transistors are connected in series. Then there is a path to from the output to Gnd only when both transistors are on. If the output should be low if either of the inputs are on, then we should create a circuit where the two transistors are put in parallel, where the source of both transistors goes to Gnd, and the drain of both transistors connects to the output. In this case when either transistor is on, the output will be connected to Gnd. What conditions should cause the output to be 1? We use the answer to create the pMOS transistor circuit that connects the output to Vdd. If two inputs both must be LOW for the output to HIGH, then we need to create a circuit that only connects the outputs when both transistors are on. This condition occurs when the two transistors are connected in series. Then there is a path to from the output to Vdd only when both transistors are on. If the output should be HIGH if either
You've reached the end of your free preview.
Want to read all 244 pages?
- Spring '19
- Hassan Kasfy