Strip off oxide to complete patterning step n well p

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Strip off oxide to complete patterning step n well p substrate n+ n+ n+ 43/111 0: Introduction
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Digital IC P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p substrate n well n+ n+ n+ p+ p+ p+ 44/111 0: Introduction
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Digital IC Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+ n+ n+ p+ p+ p+ Contact 45/111 0: Introduction
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Digital IC Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+ n+ n+ p+ p+ p+ Metal 46/111 0: Introduction
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Digital IC Two Types of MOSFETs nMOSFET(n-channel) Gate Source Drain p-type silicon substrate n + n + Sourc e Drain Gate Substrate pMOSFET(p-channel) Source Gate Drain p + p + n-type silicon substrate Source Gate Drain Substrate 47 0: Introduction
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Digital IC Circuit Under Design V DD V DD V in V out M 1 M 2 M 3 M 4 V out 2 48 0: Introduction
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Digital IC Its Layout View 49 0: Introduction
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Digital IC Semiconductor processing Semiconductor fabrication Layout fundamental Semiconductor testing Semiconductor assembling 50/111 0: Introduction
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Digital IC Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts 51/111 0: Introduction
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