# B implement the complementary cmos logic for the

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b) Implement the complementary CMOS logic, for the expression Y=A· (B+C) + (D+E). Dec-12 05-Marks each 3.Discuss the merits & demerits of following CMOS logic structures with a two inputNAND gate realization as an example. i) CMOS domino logic ii) PseudoNMOS logic iii) Dynamic CMOS logic(Dec-08/Jan-09)10 marks 4.Explain the following logic structures with their salient features: A. Bi-CMOS logic B. Pseudo-nMOS logic (Jul 2011)10 marks 5.Explain the following logic structures with their salient features: A. Pass transistor logic 6.a) Explain 2-input x-nor gate in pass transistor logic. b) Realize Z=A (B+C) +DE for a clocked CMOS logic. (June-2012) 5 marks 7.Explain the working of BiCMOS NAND.(Jan 2014) 10 marks
8.Explain the circuit of dynamic CMOS logic by taking an example of the function Y= AB+C(Dec 2013/Jan 2014) 10 marks 9.Discuss the working, merits and demerits of the following logic structures with two i/pNAND gate realization as an example: i) Pseudo NMOS logic (ii) ComplementaryCMOS logic. Jul 2014 10 marks 10. Explain the differences between CMOS complementary logic and BICMOS logic.11. Explain Dynamic logic and Clocked CMOS logic. Jan 2015 10 marks 12. a) What are the properties of nMOS and pMOS switches? How is transmission gateuseful? Jun 2012 5 marks b) Find the equations for node voltages V1, V2, V3 during logic ‘1’ transfer. AssumethresholdvoltageofeachtransistorasVtn.13. Discuss the operation of Dynamic CMOS logic and the problem of cascading in it. 5 Dec 2012
Module 4: 1.Discuss the limitation of scaling. (10-Marks)2.Derive the expression total delay for N stage of NMOS & CMOS inverters by assuming the width factor f=e. (Dec-2010) (10-Marks)3.a) Two nMOS inverters are cascaded drive capacitive load CL=16 Cgas shown in fig. Calculate pair delays Vin to Voutin terms of τ. Dec 2008 (05-Marks)b)Define sheet resistance & standard unit of capacitance Cg. Calculate the ON resistance fornMOS inverter with Rsn=10 kΩ, Zpu=4 & Zpd=1. 4.Explain the terms: i) Rise time ii) Fall time iii) Delay time. 5.Define sheet Resistance (Rs) and standard unit of capacitance (1 Cg).Calculate the onresistance of 4:1 nmos inverter with Rs=10KΩ/ .Zpu=8λ/2λ,zpd=2λ/2λ.6.a) A particular layer of MOS circuit has a resistivity of 10 ohm-cm.A section of this layer