# Respectively depart considerably from their ideal

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respectively, depart considerably from their ideal values. Mapping these levels to the output,

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 780 (1) 780 Chap. 15 Digital CMOS Circuits we observe that also exhibits degraded logical levels. In a chain of gates, such successive degradations may make the system very “fragile” and even completely corrupt the states. Example 15.5 Sketch the small-signal voltage gain for the characteristic shown in Fig. 15.4 as a function of . Solution The slope of the VTC begins from zero, becomes more negative above , and approaches zero again for . Figure 15.7 plots the result. in V 0 V DD out dV in dV Figure 15.7 Exercise Is this plot necessarily symmetric? Use an CS stage as an example. Example 15.6 Prove that the magnitude of the small-signal gain obtained in Example 15.5 must exceed unity at some point. Solution Superimposing a line with a slope of on the VTC as shown in Fig. 15.8, we note that the in V V out V DD V DD 1 Figure 15.8 slope of the VTC is sharper than unity across part of the transition region. This is because the transition region spans a range narrower than 0 to . Exercise An inverter exhibits a gain of about 2 in its transition region. How wide is the transition
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 781 (1) Sec. 15.1 General Considerations 781 region? Noise Margin In order to quantify the robustness of a gate with respect to the degradation of the input logical levels, we introduce the concept of “noise margin” (NM). A rough definition is: NM is the maximum amount of degradation (noise) at the input that can be tolerated before the output is affected “significantly.” What do we mean by “significantly?” We postulate that the output remains relatively unaffected if the gain of the circuit remains below unity, thus arriving at the following definition: The noise margin is the maximum departure from the ideal logical level that places the gate at a small-signal voltage gain of unity. The procedure for calculating NM is straightforward: we construct the VTC and determine the input level at which the small-signal gain reaches unity. The difference between this level and the ideal logical level yields the NM. Of course, we associate a noise margin with the input low level, , and another with the input high level, . Figure 15.9 summarizes these in V V out V DD V DD V V 1 1 IL IH NM L NM H Figure 15.9 Illustration of noise margins. concepts. The two input voltages are denoted by and , respectively. Example 15.7 A common-source stage operates as an NMOS inverter. Compute the noise margins. Solution We can adopt one of two approaches here. First, since the small-signal gain of the stage is equal to and since , we have (15.7) and hence (15.8) In the second approach, we directly differentiate both sides of Eq. (15.2) with respect to : (15.9) (15.10)

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 782 (1) 782 Chap. 15 Digital CMOS Circuits and hence (15.11) That is, the input must exceed by
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