# V r dd d out v m 1 v b in m 2 x r s in v g 1 v x m2 g

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V R DD D out V M 1 V b in M 2 X R S in v g 1 v X m2 g 1 m1 M 1 R S r R O1 out1 g 1 m2 r O2 (c) (a) (b) R S V Figure 7.26 (a) Example of CG stage, (b) equivalent input network, (c) calculation of output resistance. Solution We first compute with the aid of the equivalent circuit depicted in Fig. 7.26(b): (7.111) (7.112) Noting that , we have (7.113)

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 344 (1) 344 Chap. 7 CMOS Amplifiers To compute the output impedance, we first consider , as shown in Fig. 7.26(c), which from (7.110) is equal to (7.114) (7.115) The overall output impedance is then given by (7.116) (7.117) Exercise Calculate the output impedance if the gate of is tied to a constant voltage. 7.3.1 CG Stage With Biasing Following our study of the CB biasing in Chapter 5, we surmise the CG amplifier can be biased as shown in Fig. 7.27. Providing a path for the bias current to ground, resistor lowers the input impedance—and hence the voltage gain—if the signal source exhibits a finite output impedance, . V R DD D out V M 1 R 2 R 1 R 3 C 1 in V R X S Figure 7.27 CG stage with biasing. Since the impedance seen to the right of node is equal to , we have (7.118) (7.119) where channel-length modulation is neglected. As mentioned earlier, the voltage divider consist- ing of and does not affect the small-signal behavior of the circuit (at low frequencies). Example 7.14 Design the common-gate stage of Fig. 7.27 for the following parameters: ,
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 345 (1) Sec. 7.3 Common-Gate Stage 345 , , , power mW, V. Assume , V, and . Solution From the power budget, we obtain a total supply current of 1.11 mA. Allocating 10 A to the voltage divider, and , we leave 1.1 mA for the drain current of . Thus, the voltage drop across is equal to 550 mV. We must now compute two interrelated parameters: and . A larger value of yields a greater , allowing a lower value of . As in Example 7.11, we choose an initial value for to arrive at a reasonable guess for . For example, if V, then , and , dictating for . Let us determine whether operates in saturation. The gate voltage is equal to plus the drop across , amounting to 1.35 V. On the other hand, the drain voltage is given by V. Since the drain voltage exceeds , is indeed in saturation. The resistive divider consisting of and must establish a gate voltage equal to 1.35 V while drawing 10 A: (7.120) (7.121) It follows that and . Exercise If cannot exceed 100, what voltage gain can be achieved? Example 7.15 Suppose in Example 7.14, we wish to minimize (and hence transistor capacitances). What is the minimum acceptable value of ? Solution For a given , as decreases, increases. Thus, we must first compute the maximum allowable . We impose the condition for saturation as (7.122) where denotes the voltage drop across , and set to the required gain: (7.123) Eliminating from (7.122) and (7.123) gives: (7.124)

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 346 (1) 346 Chap. 7 CMOS Amplifiers and hence (7.125) In other words, (7.126) It follows that (7.127) Exercise Repeat the above example for .
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