Checks whether the page number is larger than value in page table length

Checks whether the page number is larger than value

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Checks whether the page number is larger than value in page table length register a. If it is MMU raises an exception 3) Otherwise, MMU uses the page table to determine the frame number of the frame that holds the virtual page and combine the frame number and offset to determine the physical address Page Table Entries - Primary payload: frame number - Typically contain other information as well: o Info provided by kernel – to control address translation by MMU, such as: Valid bit: Is process permitted to use this part of the addrspace? Present bit: Is the page mapped into physical memory? Protection bits o Info provided by MMU – to help kernel manage addrspaces, such as: Reference (use) bit: Has the process used this page recently? Dirty bit: Has the process changed the contents of this page? - During address translation, MMU checks to ensure that the process uses only valid virtual addresses. - May also enforce other protection rules o Typically, each PTE contains a READ-ONLY bit that indicates whether the corresponding page may be modified by the process - If these rules are violated MMU raises an exception handled by kernel
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Summary… - Kernel o Manages MMU state on addrspace switches (context switches) o Creates and manages the page tables o Manages (allocates/deallocates) physical memory o Handles exceptions raised by MMU - MMU (hardware) o Translates virtual addresses to physical addresses o Checks for and raises exceptions when necessary Speed of Address Translation - Include a TRANSLATION LOOKASIDE BUFFER (TLB) in MMU o Fast, fully associative address translation cache o TLB avoids a page table lookup TLB - Each entry in the TLB contains a (page number, frame number) pair - TLB Hit – If address translation can be accomplished using a TLB entry - TLB Miss – Otherwise - If MMU cannot distinguish TLB entries from different addrspaces. then the kernel must clear or invalidate the TLB on each addrspace switch. - May be hardware-controlled or software-controlled Hardware-controlled TLB - MMU finds the frame number by page table lookup, translates the virtual address, and adds the translation (page number, frame number pair) to the TLB. - If TLB is full MMU evicts an entry to make room for the new one Software-controlled TLB - MMU causes an exception kernel exception handler to run - Kernel must determine the correct page-to-frame mapping and load the mapping into the TLB (evict an entry if full) return from exception - MMU retries the instruction that caused the exception Virtual Address Space - 0 to 4MB-1: reserved for NULL pointers or attempts to index into an array that has not yet been allocated - 4MB to 256MB-1: Reserved for code and READ-ONLY data - 256MB up: Reserved for data - 2BG-1 down: Reserved for stack Sizes….
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- Size of the user address space for OS/161 with MIPS processor is 2 31 bytes - Size of a page is 4KB or 2 12 bytes Takes 2 31 /2 12 = 2 19 different pages for a single user process - If each page table entry is 4 bytes, then size of the page table for each process is 4*2
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