Write register write data read data 1 read data 2

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Unformatted text preview: Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15: 1 ] M u x 1 M u x 1 1 Instruction [7: 0] Instruction [25: 21] Instruction [20: 16] Instruction [15: 0] Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite[3:0] ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5: 0] Instruction [31:26] Instruction [5: 0] M u x 2 Jump ad res Instruction [5: 0] 6 8 Shift left 2 1 1 M u x 3 2 M u x 1 ALUOut Memory MemData Write data Ad res PCEn ALUControl • Divide and Conquer – Create Hierarchy – Organize system recursively into modules • Regularity – Reuse modules wherever possible – Ex: Standard cell library • Modularity : – Create well-formed interfaces – Allows modules to be treated as black boxes • Locality – Physical and temporal MIPS Floorplan and Layout datapath 2700 λ x 1050 λ (2.8 M λ 2) alucontrol 200 λ x 100 λ (20 k λ 2) zipper 2700 λ x 250 λ 2700 λ 1690 λ wiring channel: 30 tracks = 240 λ mips (4.6 M λ 2) bitslice 2700 λ x 100 λ control 1500 λ x 400 λ (0.6 M λ 2) 3500 λ 3500 λ 5000 λ 5000 λ 10 I/O pads 10 I/O pads 10 I/O pads 10 I/O pads Pitch Matching • Synthesized controller area is mostly wires – Design is smaller if wires run through/over cells...
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  • Spring '10
  • bashir
  • Central processing unit, Processor register, Standard cell, I/O pads, wiring tracks, Design Partitioning

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