Potential speed advantage because logic is performed

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Potential speed advantage because logic is performed with nMOS transistors Cross-coupled load sizing – Large pMOS will slow down transition (similar to Pseudo NMOS) – Small pMOS slows lo-to-hi transition Does not work well for wide NOR gates – CVSL requires the complement funciton (slow tall NAND pull-down) XOR
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6 Pass Transistor Logic Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates B B A F = AB 0 V DD In Out x 0.5 m/0.25 m 0.5 m/ 0.25 m 1.5 m/ 0.25 m 0 0.5 1 1.5 2 0.0 1.0 2.0 3.0 Time [ns] Volt age [V] x Out In N Transistor No Static power dissipation Level Restoring Transistor Full Swing Restorer adds capacitance, takes away pull down current at X Ratio Problem Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack 0 100 200 300 400 500 0.0 1.0 2.0 W / L r =1.0/0.25 W / L r =1.25/0.25 W / L r =1.50/0.25 W / L r =1.75/0.25 Vo lt ag e [V] Time [ps] 3.0 M 2 M 1 M n Out A B V DD LEAP and CPL •L E A n integration with P ass transistors Get rid of pMOS transistors – Use weak pMOS feedback to pull fully high – Ratio constraint •C omplementary P ass- transistor L ogic – Dual-rail form of pass transistor logic – Optional cross-coupling for rail- to-rail swing B S S A Y L B S S S S A B A Y Y L L Ganged CMOS, SFPL, Multidrain Logic Source Follower Pull-up Logic Ganged CMOS
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  • Spring '08
  • Bashirullah
  • Gate, Logic gate, GD, logical effort

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