S in this scheme every datainstruction access

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s In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. s The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
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Silberschatz, Galvin and Gagne 2002 9.26 Operating System Concepts Associative Memory s Associative memory – parallel search Address translation (A´, A´´) h If A´ is in associative register, get frame # out. h Otherwise get frame # from page table in memory Page # Frame #
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Silberschatz, Galvin and Gagne 2002 9.27 Operating System Concepts Paging Hardware With TLB
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Silberschatz, Galvin and Gagne 2002 9.28 Operating System Concepts Effective Access Time s Associative Lookup = ε time unit s Assume memory cycle time is 1 microsecond s Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers. s Hit ratio = α s Effective Access Time (EAT) EAT = (1 + ε ) α + (2 + ε )(1 – α ) = 2 + ε α
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Silberschatz, Galvin and Gagne 2002 9.29 Operating System Concepts Memory Protection s Memory protection implemented by associating protection bit with each frame. s Valid-invalid bit attached to each entry in the page table: h “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page. h “invalid” indicates that the page is not in the process’ logical address space.
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Silberschatz, Galvin and Gagne 2002 9.30 Operating System Concepts Valid (v) or Invalid (i) Bit In A Page Table
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Silberschatz, Galvin and Gagne 2002 9.31 Operating System Concepts Page Table Structure s Hierarchical Paging s Hashed Page Tables s Inverted Page Tables
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Silberschatz, Galvin and Gagne 2002 9.32 Operating System Concepts Hierarchical Page Tables s Break up the logical address space into multiple page tables. s A simple technique is a two-level page table.
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Silberschatz, Galvin and Gagne 2002 9.33 Operating System Concepts Two-Level Paging Example s A logical address (on 32-bit machine with 4K page size) is divided into: h a page number consisting of 20 bits. h a page offset consisting of 12 bits. s Since the page table is paged, the page number is further divided into: h a 10-bit page number. h a 10-bit page offset. s Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table. page number page offset p i p 2 d 10 10 12
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Silberschatz, Galvin and Gagne 2002 9.34 Operating System Concepts Two-Level Page-Table Scheme
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Silberschatz, Galvin and Gagne 2002 9.35 Operating System Concepts Address-Translation Scheme s Address-translation scheme for a two-level 32-bit paging architecture
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Silberschatz, Galvin and Gagne 2002 9.36 Operating System Concepts Hashed Page Tables s Common in address spaces > 32 bits. s
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s In this scheme every datainstruction access requires two...

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