Square6 page table base register ptbr points to the

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Page table is kept in main memory. square6 Page-table base register ( PTBR) points to the page table. square6 Page-table length register (PRLR) indicates size of the page table. square6 In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. square6 The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
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Silberschatz, Galvin and Gagne 2002 9.26 Operating System Concepts Associative Memory square6 Associative memory – parallel search Address translation (A´, A´´) handptright If A´ is in associative register, get frame # out. handptright Otherwise get frame # from page table in memory Page # Frame #
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Silberschatz, Galvin and Gagne 2002 9.27 Operating System Concepts Paging Hardware With TLB
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Silberschatz, Galvin and Gagne 2002 9.28 Operating System Concepts Effective Access Time square6 Associative Lookup = ε time unit square6 Assume memory cycle time is 1 microsecond square6 Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers. square6 Hit ratio = α square6 Effective Access Time (EAT) EAT = (1 + ε ) α + (2 + ε )(1 – α ) = 2 + ε α
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Silberschatz, Galvin and Gagne 2002 9.29 Operating System Concepts Memory Protection square6 Memory protection implemented by associating protection bit with each frame. square6 Valid-invalid bit attached to each entry in the page table: handptright “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page. handptright “invalid” indicates that the page is not in the process’ logical address space.
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Silberschatz, Galvin and Gagne 2002 9.30 Operating System Concepts Valid (v) or Invalid (i) Bit In A Page Table
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Silberschatz, Galvin and Gagne 2002 9.31 Operating System Concepts Page Table Structure square6 Hierarchical Paging square6 Hashed Page Tables square6 Inverted Page Tables
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Silberschatz, Galvin and Gagne 2002 9.32 Operating System Concepts Hierarchical Page Tables square6 Break up the logical address space into multiple page tables. square6 A simple technique is a two-level page table.
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Silberschatz, Galvin and Gagne 2002 9.33 Operating System Concepts Two-Level Paging Example square6 A logical address (on 32-bit machine with 4K page size) is divided into: handptright a page number consisting of 20 bits. handptright a page offset consisting of 12 bits. square6 Since the page table is paged, the page number is further divided into: handptright a 10-bit page number. handptright a 10-bit page offset. square6 Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table.
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