Basic Computer Organization and Design 32 CSE 211 Memory Reference Instructions

Basic computer organization and design 32 cse 211

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Basic Computer Organization and Design 32 CSE 211 Memory Reference Instructions AND to AC //performs AND logic with AC and memory word specified by EA D 0 T 4 : DR M[AR] Read operand D 0 T 5 : AC AC DR, SC 0 AND with AC - The effective address of the instruction is in AR and was placed there during timing signal T 2 when I = 0, or during timing signal T 3 when I = 1 - Memory cycle is assumed to be short enough to complete in a CPU cycle - The execution of MR instruction starts with T 4 Symbol Operation Decoder Symbolic Description AND D 0 AC AC M[AR] ADD D 1 AC AC + M[AR], E C out LDA D 2 AC M[AR] STA D 3 M[AR] AC BUN D 4 PC AR BSA D 5 M[AR] PC, PC AR + 1 ISZ D 6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
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Basic Computer Organization and Design 33 CSE 211 Memory Reference Instructions ADD to AC // add content of memory word specified by EA to value of AC sum is transferred to AC and Carry to E (Extended Accumulator) D 1 T 4 : DR M[AR] Read operand D 1 T 5 : AC AC + DR, E C out , SC 0Add to AC and store carry in E LDA: Load to AC // Transfers memory word specified by memory address to AC D 2 T 4 : DR M[AR] D 2 T 5 : AC DR, SC 0 STA: Store AC // Stores the content of AC into memory specified by EA D 3 T 4 : M[AR] AC, SC 0 BUN: Branch Unconditionally // Transfer program to instruction specified by EA D 4 T 4 : PC AR, SC 0
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Basic Computer Organization and Design 34 CSE 211 Memory Reference Instructions Memory, PC after execution 21 0 BSA 135 Next instruction Subroutine 20 PC = 21 AR = 135 136 1 BUN 135 Memory, PC, AR at time T4 0 BSA 135 Next instruction Subroutine 20 21 135 PC = 136 1 BUN 135 BSA: Branch and Save Return Address // 1. stores address of next instruction in sequence (PC) into address specified by EA 2. EA+1 transfer to PC serve as 1 st inst. In subroutine M[AR] PC, PC AR + 1 BSA : D 5 T 4 : M[AR] PC, AR AR + 1 D 5 T 5 : PC AR, SC 0 BSA: Example M[135] 21, PC 135 + 1=136
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Basic Computer Organization and Design 35 CSE 211 Memory Reference Instructions ISZ: Increment and Skip-if-Zero // increments the word specified by effective address, and if incremented value=0 , PC incremented by 1 D 6 T 4 : DR M[AR] D 6 T 5 : DR DR + 1 D 6 T 4 : M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0
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Basic Computer Organization and Design 36 CSE 211 Flow Chart - Memory Reference Instructions Memory-reference instruction DR M[AR] DR M[AR] DR M[AR] M[AR] AC SC 0 AND ADD LDA STA AC AC DR SC 0 AC AC + DR E Cout SC 0 AC DR SC 0 D T 0 4 D T 1 4 D T 2 4 D T 3 4 D T 0 5 D T 1 5 D T 2 5 PC AR SC 0 M[AR] PC AR AR + 1 DR M[AR] BUN BSA ISZ D T 4 4 D T 5 4 D T 6 4 DR DR + 1 D T 5 5 D T 6 5 PC AR SC 0 M[AR] DR If (DR = 0) then (PC PC + 1) SC 0 D T 6 6
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Basic Computer Organization and Design 37 CSE 211 Input/Output and Interrupt Input-Output Configuration INPR Input register - 8 bits OUTR Output register - 8 bits FGI Input flag - 1 bit FGO Output flag - 1 bit IEN Interrupt enable - 1 bit - The terminal sends and receives serial information - The serial info. from the keyboard is shifted into INPR
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