MidtermExam_2009

# You may assume that rising clock edges trigger both

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(You may assume that rising clock edges trigger both the change of state, and the new input value, with both changes occurring a short delay time later after the clock edge.) Output Z should be 1 if the last 3 bits seen on A have been 010, and the current value of A is 1; Z should be 0 otherwise. a) Give the state diagram for your system (drawing the states in a row from left to right across the page, and naming the states S 0 , S 1 , S 2 … accordingly). b) After making a Gray code state assignment, give the state table (using state codes) for your system. Let present state variables be named X n , …X 0 , where X 0 is the least significant bit of the state code. [Be sure to write your state table in standard form, NOT in the shortened two-dimensional form.] c) Prepare to implement the sequence recognizer in digital hardware, using positive-edge triggered JK-type flip flops and gates. Rather than draw the circuit diagram with JK flip-flops and gates, you should simply give the minimized 2-level Boolean SOP equations for the flip-flop input functions, and for the output function, in terms of present state variables and input variable.
• Fall '13
• MehmetBaray
• Finite State Machines, gate input cost

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