Processing advantages: No Field Oxide (an channel stop implant) needed No Well needed for NMOS and PMOS (b) (25 points) Describe your process flow in a left column and sketch and label the cross-sections of the device after each lithography step in a right column. The process flow is similar to a bulk CMOS process flow except no well formation and no FOX steps are needed. You have to convert one of the Si island from n-type to p-type to accommodate the NMOS. Process Description Cross-sections Starting Material: SOI substrate Process Description Cross Section The following solutions is just one of the possible solutions: Starting Material: n-Si on SOI (shown as Al203 in figures) Mask#1 Define p-region opening Boron implantation Remove resist Boron drive-in Gate oxide growth Undoped Poly-Si deposition by CVD Mask#2 Pattern poly gates for both NMOs and PMOS Buried Oxide (SiO2)Si substrateCVD oxideGate oxide (thermal SiO2)CVD oxideCVD oxide
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11Mask#3 Protect PMOS regions (alignment not critical) As implantation to form n+ S/D and n+ gate Mask#4 Protect NMOS regions (alignment not critical) Boron implantation to form p+ S/D and p+ gate Mask #5 Define isolation area which will be etched away Reactive ion etching of epi Si CVD SiO2Mask#6 Contact hole opening Al deposition Mask#7 Al patterning