Example T T 1 T 2 T 3 T 4 T T 1 Assume At time T 4 SC is cleared to 0 if

Example t t 1 t 2 t 3 t 4 t t 1 assume at time t 4 sc

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- Example: T 0 , T 1 , T 2 , T 3 , T 4 , T 0 , T 1 , . . . Assume: At time T 4 , SC is cleared to 0 if decoder output D3 is active. D 3 T 4 : SC 0
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Basic Computer Orgsnization and Design 25 CSE 211 Instruction Cycle In Basic Computer, a machine instruction is executed in the following cycle: 1. Fetch an instruction from memory 2. Decode the instruction 3. Read the effective address from memory if the instruction has an indirect address 4. Execute the instruction After an instruction is executed, the cycle starts again at step 1, for the next instruction Note : Every different processor has its own (different) instruction cycle
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Basic Computer Organization and Design 26 CSE 211 Fetch and Decode T0: AR PC T1: IR M [AR], PC PC + 1 T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15) Initially PC loaded with address of first instruction and Sequence counter cleared to 0, giving timing signal T 0
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Basic Computer Organization and Design 27 CSE 211 Fetch and Decode Fetch and Decode T0: AR PC (S 0 S 1 S 2 =010, T0=1) T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1) T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15) S 2 S 1 S 0 Bus 7 Memory unit Address Read AR LD PC INR IR LD Clock 1 2 5 Common bus T1 T0
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Basic Computer Organization and Design 28 CSE 211 Fetch and Decode Figure shows how first two statements are implemented in bus system At T 0 : 1. Place the content of PC into bus by making S 2 S 1 S 0 =010 Transfer the content of bus to AR by enabling the LD input of AR At T 1 : 1. Enable read input of memory 2. Place content of bus by making S2S1S0=111 3. Transfer content of bus to IR by enabling the LD input of IR 4. Increment PC by enabling the INR input of PC
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Basic Computer Organization and Design 29 CSE 211 Determine the Type of Instructions = 0 (direct) Start SC <-- 0 AR <-- PC T0 IR <-- M[AR], PC <-- PC + 1 T1 AR <-- IR(0-11), I <-- IR(15) Decode Opcode in IR(12-14), T2 D7 = 0 (Memory-reference) (Register or I/O) = 1 I I Execute register-reference instruction SC <-- 0 Execute input-output instruction SC <-- 0 M[AR] <-- AR Nothing = 0 (register) (I/O) = 1 (indirect) = 1 T3 T3 T3 T3 Execute memory-reference instruction SC <-- 0 T4 Fig : Flow chart for Instruction Cycle
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Basic Computer Organization and Design 30 CSE 211 Determining Type of Instruction D' 7 IT 3 : AR M[AR] D' 7 I'T 3 :Nothing D 7 I'T 3 : Execute a register-reference instr. D 7 IT 3 : Execute an input-output instr.
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Basic Computer Organization and Design 31 CSE 211 Register Reference Instruction r = D 7 I T 3 => Register Reference Instruction B i = IR(i) , i=0,1,2,...,11 - D 7 = 1, I = 0 - Register Ref. Instr. is specified in b 0 ~ b 11 of IR - Execution starts with timing signal T 3 Register Reference Instructions are identified when r: SC 0 CLA rB 11 : AC 0 CLE rB 10 : E 0 CMA rB 9 : AC AC’ CME rB 8 : E E’ CIR rB 7 : AC shr AC, AC(15) E, E AC(0) CIL rB 6 : AC shl AC, AC(0) E, E AC(15) INC rB 5 : AC AC + 1 SPA rB 4 : if (AC(15) = 0) then (PC PC+1) SNA rB 3 : if (AC(15) = 1) then (PC PC+1) SZA rB 2 : if (AC = 0) then (PC PC+1) SZE rB 1 : if (E = 0) then (PC PC+1) HLT rB 0 : S 0 (S is a start-stop flip-flop) e.g. r B 11 =CLA
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