BIT20303 Computer Architecture 16 Fakulti Sains Komputer dan Technology

Bit20303 computer architecture 16 fakulti sains

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BIT20303-Computer Architecture 16
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Fakulti Sains Komputer dan Technology Maklumat (FSKTM), UTHM Condition Code BIT20303-Computer Architecture 17
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How big register are needed? BIT20303-Computer Architecture 18
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Fakulti Sains Komputer dan Technology Maklumat (FSKTM), UTHM Control & Status Registers Four registers are essential to instruction execution: Program counter (PC): Contains the address of an instruction to be fetched Instruction register (IR): Contains the instruction most recently fetched Memory address register (MAR): Contains the address of a location in memory Memory buffer register (MBR): Contains a word of data to be written to memory or the word most recently read BIT20303-Computer Architecture 19
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Fakulti Sains Komputer dan Technology Maklumat (FSKTM), UTHM Control & Status Registers How they operate with each other : The processor updates the PC after each instruction fetch so that the PC always points to the next instruction to be executed. Skip instruction will also modify the contents of the PC . The fetched instruction is loaded into an IR , where the opcode and operand specifiers are analyzed. Data are exchanged with memory using the MAR and MBR . In a bus-organized system, the MAR connects directly to the address bus, and the MBR connects directly to the data bus. BIT20303-Computer Architecture 20
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Fakulti Sains Komputer dan Technology Maklumat (FSKTM), UTHM Program Status Word Many processor designs include a register or set of registers, often known as the Program Status Word (PSW), that contain status information. The PSW typically contains condition codes plus other status information. Common fields or flags include the following: BIT20303-Computer Architecture 21 Sign Zero Carry Equal Overflow Interrupt enable/disable Supervisor
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Fakulti Sains Komputer dan Technology Maklumat (FSKTM), UTHM Program Status Word Sign: Contains the sign bit of the result of the last arithmetic operation. Zero: Set when the result is 0. Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a high- order bit. Used for multiword arithmetic operations. Equal: Set if a logical compare result is equality. BIT20303-Computer Architecture 22
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Fakulti Sains Komputer dan Technology Maklumat (FSKTM), UTHM Program Status Word Equal: Set if a logical compare result is equality. Overflow: Used to indicate arithmetic overflow. Interrupt Enable/Disable: Used to enable or disable interrupts. Supervisor: Indicates whether the processor is executing in supervisor or user mode. Certain privileged instructions can be executed only in supervisor mode, and certain areas of memory can be accessed only in supervisor mode.
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