RAM Modeling Output Enables RAM Modeling Output Enables z Example 1 A level

Ram modeling output enables ram modeling output

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RAM Modeling: Output Enables* RAM Modeling: Output Enables* z Example #1: A level sensitive read port enabled by read=1 with a separate tri-state output enabled by OEB=0.. z Examples #2: An edge sensitive read port with separate tri-state output enabled by OEB=0. output [7:0] data_out; reg [7:0] data_out, data_reg; /* add data_reg */ always @(read or read_addr or WRITE_OP) if (read) data_reg = memory[read_addr]; always @(OEB or data_reg) if (!OEB) data_out = data_reg; else data_out = 8'bZZZZZZZZ; output [7:0] data_out; reg [7:0] data_out, data_reg; /* add data_reg */ and u1 (RCLK, read, CS); always @(posedge RCLK) data_reg = memory[read_addr]; always @(OEB or data_reg) if (!OEB) data_out = data_reg; else data_out = 8'bZZZZZZZZ;
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2002 / Summer CIC -- Design-for-Testability 225 RAM Completed Example* RAM Completed Example* A completed example with an edge controlled write port , a level sensitive read port , and a separate output enable . module ATPG_RAM (CS, OE, read, write, data_in, data_out, addr); input CS, OE, read, write; input read, write; input [7:0] data_in; // 8 bit data width input [3:0] addr; // 16 words output [7:0] data_out; // module outputs output [7:0] data_reg; // RAM outputs reg [7:0] data_out; // output holding register reg [7:0] memory [0:15] ; // memory storage event WRITE_OP; . and u1 (REN, !read, CS); // form read enable and u2 (TSO, OE, CS); // form tri-state out control . always @(posedge write) if (CS) begin memory[addr] = data_in; #0; ->WRITE_OP; end . always @(REN or addr or WRITE_OP) if (REN) data_reg = memory[addr] . always @(TSO or data_reg) if (TSO) data_out = data_reg; else data_out = 8'bzzzzzzzz; endmodule
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2002 / Summer CIC -- Design-for-Testability 226 ROM Modeling* ROM Modeling* z A ROM is modeled identically to a RAM with these exceptions z it has no write ports z it requires an initialization file z Here's a simple ROM with a tri-state output enable. module MY_ROM ( oe, addr, data_out ); input oe; // output control input [3:0] addr; // 16 words output [7:0] data_out; // 8 bits per word reg [7:0] data_out; // output holding reg reg [7:0] memory [0:15] ; // memory storage always @(oe or addr) if (!oe) data_out = memory[addr]; else data_out = 8'bZZZZZZZZ; initial $readmemh("rom_image.dat", memory); end module
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2002 / Summer CIC -- Design-for-Testability 227 RAM/ROM data files* RAM/ROM data files* z ROM models require a memory initialization file and RAM models may also use them. z The format is standard Verilog and supports some flexibilities in how data can be presented. 0001 0002 0004 0008 0010 0020 0040 0080 0100 0200 0400 0800 1000 2000 4000 8000 // address = 0010 A001 c401 e404 700a 3816 1c2c 2e58 07b0 23e0 07c0 25e0 0b70 363c 2c1c 7c0e b006 8001 4002 2004 1008 8810 4421 2242 1184 0908 0650 0620 0950 1088 // skip loading next 3 addresses @30 // address = 0030 fffe fffd fffb fff7 ffef ffdf ffbf ff7f feff fdff fbff f7ff // end of line comment // underscores for readability ef_ff df_ff bf_ff 7f_ff
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TetraMAX TetraMAX Lab 7 Lab 7 RAM Modeling RAM Modeling
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Design Design - - for for - - Testability Testability ATPG with ATPG with TetraMAX TetraMAX Debugging Problems Debugging Problems
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2002 / Summer CIC -- Design-for-Testability 230 Defining Input Masks Defining Input Masks z Input masks are accomplished by defining a PI constraint of X on an input .
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