computer architecture Flashcards

Terms Definitions
Why should you design a system with a hierarchy of buses over a single bus ?
Propagation delays are reduced- More total drives can be spread across the busesor - each bus can have its own speed relative to the speed of the devices on the bus
What is a disadvantage of direct mapping ?
fixed chache for any given block which causes low hit ratio known as "thrashing"
describe the key features of an interrupt cycle
portion of the instruction cycle which the cpu checks for interuppts, if an interuppt in pending then the cpu saves the current program state and resumes processing at an interrupt/handler routine
what are the two write policies ? give a short explanations
1. WRITE THROUGH - operations are written to main memory and cache2. WRITE BACK - operations written to cache
what are the strategies of exploiting spacial and temperal locality ?
locality of reference - the tendency of a process to access the same set of memory locations repetitively over a short period of time
what is the Von neuman machine ?
stored program concept. program loaded into main mem. instructions are fetched, decoded, and executed from main mem
what are the technical advantages of having a family architecture E.G. x86, sun, sparc, IBM 360 series
different series have different strengths depending on what type of machine you're developing one might be more beneficial than the other
what is the objective of this course ?
to learn the functions and architecture of different parts of a computer memory such as registers and the cpu
explain the functioning of synchronis and asynchronis data transfer
synchronis data transfer functions sequentially by transfering data one after the other (at clock pulses) asynchronis data transfers does not function sequentially, it transfers data randomly (between clock pulses)
what is the differences among sequencial, direct, and random accesses ?
sequencial access is data thats accessed one after the otherdirect - is a particular portion of data is accessed directly.random - data is accessed in random order
A set associative cache has a block size of two 16-bi words and a set size of 4. The chache can accommodate a total of 4K 32-bit words from the main memory. the proessor data bus is 16-bits and issues 24-bit addresses. Design the cache structure, by a
hmk4 #4 just change tag set word to 12,10,2 respectivly
If the effective access time is 10% greater than the cache access time, what is the hit ratio ? cache access time = 100ns, main memory access time = 1200ns
(0.10 x 100) = (1-H)1200solve for H, the hit ratio
consider the following code:for(I-0;I for(j=0;j a[I] = a[I]*j;Give example of spatial & temporal locality in the code
SPATIAL - A reference to the first instruction is immediately followed by a reference to thesecond.TEMPORAL - The ten accesses to a[i] within the inner for loop which occur within a short interval of time.
In the Intel architecture, the addresses are staggered into two separate units (e.g. all even addressed words in one unit and odd ones in another). What might be the purpose of this technique?
Double Words can be accessed (in parallel) in the same time required to access a Word. In this case, SPEED has not increased, THROUGHPUT has increased.
what do the words MAR, MBR, IBR stand for?
MAR: Memory Address Register MBR: Memory Buffer Register IBR: Instruction Buffer Register
Go back to HW 1 Question 1a) What is the max. directly addressable memory capacity (in bytes)?
2^24 = 16M bytes
Go back to HW 1 Question 1b.Discuss the impact on the system speed if the microprocessor has: (i) a 32-bit local address bus and a 16-bit local data bus, or (ii) a 16-bit local address bus and a 16-bit local data bus.
b1: If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory. However, since the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction operand.b2: The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part (since the microprocessor will end in 2 steps). For a 32-bit address, one may assume the first half will decode to access a “row” in memory, while the second half is sent later to access a “column” in memory. In addition to the 2 step address operation, the microprocessor will need 2 cycles to fetch the 32-bit instruction/operand.
Go back to HW 1 Question 1c. How many bits are needed for the program counter and the instruction register?
c: The PC must be at least 24 bits. Typically, a 32-bit microprocessor will have a 32-bit external address bus and a 32-bit program counter, unless on-chip segment registers are used that may work with a smaller program counter. If the IR is to contain the whole instruction, it will have to be 32 bits long. If it will contain the op code (called the op code register) then it will have to be 8 bits long.
Go back to HW 1 Question 2a. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?
a,b: For both problems, the microprocessor will be able to access 2^16 (64K)bytes; the only difference is that with an 8-bit memory each access will transfer a byte, while with a 16-bit memory, an access may transfer a byte or a 16-bit word.
Go back to HW 1 Question 2b. What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”?
a,b: For both problems, the microprocessor will be able to access 2^16 (64K)bytes; the only difference is that with an 8-bit memory each access will transfer a byte, while with a 16-bit memory, an access may transfer a byte or a 16-bit word.
Go back to HW 1 Question 2c. What architectural features will allow this microprocessor to access a separate “I/O space”?
c: Separate input and output instructions are needed whose execution will generate separate input and output signals (different from memory signals generated by executing memory-type instructions). At a minimum, this will require an additional output pin to carry the signal.
Go back to HW 1 Question 2d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports?
'd1,2': 2^8 = 256 input and output ports
Go back to HW 1 Question 3
1: clock cycle = 8MHz^(-1) = 125nsbus cycle = 4*125ns = 500ns2 bytes transfered every 500nstransfer rate = 4M bytes/sec2: Doubling the frequency may mean adopting a new chip manufacturing technology (assuming each instruction will require the same number of clock cycles). Doubling the external bus means wider (maybe newer) on-chip data bus drivers/latches and modifications to the bus control logic. In the first case, the speed of he memory chips will also need to be doubled (roughly) in order not to slow down the microprocessor. In the second case, the “word length” of the memory will have to double to be able to send/receive 32 bit quantities.
1.What are the advantages of a hierarchy of buses has over single bus architecture?
- Propagation delays are reduced- More total drives can be spread across the busesor - each bus can have its own speed relative to the speed of the devices on the bus
Consider two microprocessors having 8- and 16-bit wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. By what factor do the maximum data transfer rates differ?
a: During a single bus cycle, the 8-bit microprocessor transfers one byte while the 16-bit microprocessor transfers two bytes. The 16-bit microprocessor has twice the data transfer rate.
Consider two microprocessors having 8- and 16-bit wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long.Repeat assuming that half of the operands and instructions are one byte long.
b: Suppose we do 100 transfers of operands and instructions, of which 50 are one byte long and 50 are two bytes long. The 8-bit microprocessor takes 50+(2x50) = 150 bus cycles for the transfer. The 16-bit microprocessor requires 50+50 = 100 bus cycles. Thus, the data transfer rates differ by a factor of 1.5.
List and briefly define two approaches of dealing with multiple interrupts.
Disabling Interrupts, Prioritize Interrupts………
What are the benefits of using a hierarchy of buses over a single bus. Find the common bus architectures in use today in PCs.
Reduce propagation delays; allow more drivers to be spread across buses; allow each bus to have its own speed.
3. What is a stored program computer?
In a stored program computer, programs are represented in a form suitable for storing in memory alongside the data. The computer gets its instructions by reading them from memory, and a program can be set or altered by setting the values of a portion of memory.
Explain Moore’s Law.
Moore observed that the number of transistors that could be put on a single chip was doubling every year and correctly predicted that this pace would continue into the near future.
On the IAS, describe the process that the CPU must undertake to read a value from memory and to write a value to memory in terms of what is put in MAR, MBR, address bus, data bus and control bus.
To read a value from memory, the CPU puts the address of the value it wants into the MAR. The CPU then asserts the Read control line to memory and places the address on the address bus. Memory places the contents of the memory location passed on the data bus. This data is then transferred to the MBR. To write a value to memory, the CPU puts the address of the value it wants to write into the MAR. The CPU also places the data it wants to write into the MBR. The CPU then asserts the Write control line to memory and places the address on the address bus and the data on the data bus. Memory transfers the data on the data bus into the corresponding memory location.
A common measure of performance for a processor is the rate at which instructions are executed, expressed in MIPS. Express MIPS rate in terms of clock rate and CPI.
MIPS rate = f / (CPI ε 10­­6)
A benchmark program is run on a 40 MHz processor. The object code consists of 100,000 instructions, with the following instruction mix and clock cycle counts.
CPI=1.55; MIPS rate=25.8; Execution time=3.87ms.
A 2-way set associative cache has lines of 16 bytes and a total size of 8KB. The 64 MB main memory is byte addressable. Show the format of main memory addresses.
TAG: 14 SET: 8 WORD: 4
For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show the following information, in hexadecimal format:Tag, line, and word values for a direct-mapped cache.
Go back to HW 4 Solutions. # 4.3
For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show the following information, in hexadecimal format:c) Tag, set, and word values for a 2-way set associative cache.
GO back to HW 4 4.3
For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show the following information, in hexadecimal format:b) Tag and word values for an associative cache.
GO back to HW 4 4.3
Go to HW 4 # 3
GO back to HW 4 Solutions
GO to HW 4 # 4
Go back to HW 4 Solutions
Suggest reasons why RAMs traditionally have been organized as only one bit per chip whereas ROMs are usually organized with multiple bits per chip.
The 1-bit-per-chip organization has several advantages. It requires fewer pins on the package (only one data out line); therefore, a higher density of bits can be achieved for a given size package. Also, it is somewhat more reliable because it has only one output driver. These benefits have led to the traditional use of 1-bit-per-chip for RAM. In most cases, ROMs are much smaller than RAMs and it is often possible to get an entire ROM on one or two chips if multiple-bits-per-chip organization is used. This saves on cost and is sufficient reason to adopt that organization.
GO back to HW 5 Question 2
In 1 ms, the time devoted to refresh is 64*150ns = 9600ns. The fractionof time devoted to memory refresh is (9.6s*10^(-6))/(10s^(-3))=0.0096 or almost 1%.1 sec = 1,000 milli = 1,000,000 micro = 1,000,000,000 nano64*150ns = 9600ns (refresh time)9600ns/1,000,000ns = 0.0096 or close to 1% of memory time
Draw the diagram of a typical 16 Mb DRAM (4M X 4) and explain its action.
Comprehensive answer can be found in Page151 in the book.
Draw the diagram of a SRAM cell and explain its action. What are the differences among EPROM, EEPROM, and flash memory?
Answer for the first part can be found in Page147.Second part: EPROM is read and written electrically; before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation. Erasure is performed by shining an intense ultraviolet light through a window that is designed into the memory chip. EEPROM is a read mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated. Flash memory is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash memory uses an electrical erasing technology. An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. However, flash memory does not provide byte-level erasure. Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM.
2.How does an SDRAM differ from a DRAM? What is a parity bit? What is burst mode (find from web)?
Unlike the traditional DRAM, which is asynchronous, the SDROM exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.A bit appended to an array of binary digits to make the sum of all the binary digits, including the parity bit, always odd (odd parity) or always even (even parity).Burst mode is a data transmission mode in which data is sent faster than normal. There are a number of techniques for implementing burst modes. In a data bus, for example, a burst mode is usually implemented by allowing a device to seize control of the bus and not permitting other devices to interrupt. In RAM, burst modes are implemented by automatically fetching the next memory contents before they are requested. This is essentially the same technique used by disk caches. The one characteristic that all burst modes have in common is that they are temporary and unsustainable. They allow faster data transfer rates than normal, but only for a limited period of time and only under special conditions. (I find this answer at http://www.webopedia.com/TERM/B/burst_mode.html . Most answers accepted. )
What are the cache formulas ?#tags ?#sets ?#words ?
#tags = #bits\#sets#sets = cache size\set size#words = address size - (tags + sets)
what does a replacement algorithm decide ?
decides which line in cache should be replaced when the cache is full and information is needed from main memory by the processor
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