Exercise 3.29
The 2-bit combinational divider from Exercise 3.23 can be implemented in verilog as
follows:
module divider(input wire A, input wire B, input wire C, input wire D,
output wire W, output wire X, output wire Y, output wire Z);
/Registers to st
Exercise 3.1
(a) f(V,W,X,Y,Z) = M(0,4,18,19,22,23,25,29)
The simplified function has 11 literals:
f = WY + VWY + VZ + VY + WZ
(b) f(A,B,C,D) = m(0,1,4,5,12,13)
The simplified function has 4 literals:
f = AC + BC
WX
YZ 00 01 11 10
00
01
11
10
V=0
WX
YZ 00
Exercise 2.27
(a) f(A, B, C) = ( A + B + C ) ( A + B + C ) ( A + B + C ) ( A + B + C )
(b) f(A, B, C) = ( A + B ) ( A + C ) ( A + B )
(c) f(A, B, C, D) = D ( A + C )
01
10
01
C10
B
A
00
01
10
C11
B
A
D
A
B
00
11
X0
X1
11
0X
00
00
C
(d) f(A, B, C, D) = ( A
Exercise 2.12
[ [ X ( XY ) ] [ Y ( XY ) ] ] = XY + XY
Using 12: [ X ( XY ) ] + [ Y ( XY ) ] = XY + XY
Using 12D: [ X ( X + Y ) ] + [ Y ( X + Y ) ] = XY + XY
Using 11: XY + XY = XY + XY
Exercise 2.13
The following figure demonstrates the implementation of
Exercise 3.11
(a) F(A,B,Cin) = AB + BCin + ACin
A
B
B
C_in
A
C_in
F
Initial Circuit
F
A
B
B
C_in
A
C_in
F
A
B
B
C_in
A
C_in
NAND Gate Implementation
A
B
B
C_in
A
C_in
F
NOR Gate Implementation
(b) F(A,B,Cin) = A xor B xor Cin
F
A
B
C
A
B
C
B
A
C
C
A
B
Ini
Exercise 5.1
(a) The input signals to this system are: # dimes and # of nickels in the reservoir, ND and
NN, respectively, and coin deposited, C. The outputs are: no change, E, # dimes and #
of nickels to return, RD and RN, respectively.
(b) ND and NN are
Exercise 4.15
This implementation uses a 2:4 decoder to enable a set of 4:16 decoders. Thus the first
16 outputs will be enabled when AB is asserted, the second 16 outputs when AB and
so on.
Exercise 4.16
Exercise 4.17
(a) Note: Due to the limitations of
Exercise 4.1
In this particular case using a K-map to simplify the problem will not be very useful since
adjacent cells in a K-map vary by only one bit, and because this is a parity function every
adjacent cell will be opposites.
Starting with the truth t
Exercise 2.1
The truth table for the functions looks as follows:
X Y Z By2 By3 By5
000111
001000
010100
011010
100100
101001
110110
111000
This translates into the following circuit. Please note that wires with the same name are
considered to be connected