The Ohio State University
Department of Electrical and Computer Engineering
ECE 5362
Theory and Computers Architecture and Design
Spring 2013
Meeting Time: 8:00am MWF, 2004 Evans Lab.
Instructor: Professor Yuan F. Zheng
Office: 720 Dreese Lab
Office Hours
ECE662 Midterm 2 - Solutions
Sp 2012
Name_
1. For each line below state if the indicated register transfers can happen in a single state in OSIAC
662. If no, explain why (20 points)
a. [T3] Q, [T5] T3
Not possible, both need bus
b. [T2] T3, [T3] SP
Not p
ECE 662 (Sp2012)
Homework 1
Due 4:30pm April 6, 2012
1. For the simple computer developed in class, consider the following program starting
in memory location 0:
0000000000001010
0010000000000011
0010000000000100
0010000000000010
0001000000000000
Write th
ECE 662 (Sp 2012)
Homework 4 Solutions
Due May 2, 2012
1.
a. T3 T2
ot3 it2
b. AC T5
rac=1 rn=0 it5
c. T1+QQ
oa oq ib oadder
d. T2+QQ
cannot be done, T2 and Q both need bus which allows one only
e. T1-T5Q
ot5 ib comp p1 oa oadder
f. Ones complement of QQ
o
ECE 662 (Sp2013)
Homework 1
Due 4:30pm January 18, 2013
1. For the simple computer developed in class, consider the following program starting
in memory location 0:
0000000000001000
0010000000000011
0010000000000100
0010000000000010
0001000000000000
Write
ECE 5362 (Sp 2013)
Homework 4
Due February 18, 2013
1.
For the OSIAC machine consider the following program (20 points)
MOVE
ADD
AND
ADD
MOVE
ADD
OR
LOOP ADD
NEG
ADD
TST
ADD
CLR
SUB
BHI
ADD
MOVE
ADD
MOVE
HALT
X, PC
SP, X
AC, X
AC, X
LA, AC
X, (AC)
X, LA
(
ECE662 (Au 2005) Machine Problem 1
Due November 5, 2005
This is the first machine problem of this course. You will run the register transfers needed to do the fetch cycle, and
execution cycles for two instructions: ADD AC,AC and HALT. You will try this ou
ECE 662 (Au2010)
Homework 1
Due 4:30pm October 4, 2010
1. For the simple computer developed in class, consider the following program starting
in memory location 0:
0000000000001010
0010000000000011
0010000000000100
0010000000000010
0001000000000000
Write
ECE 5362 (Autumn 2015)
Homework #2
Due 10:20am (before class) Sept 16, 2015 - Hardcopy
1. Registers R4 and R5 contain the decimal numbers 50 and 90 before each of the
following addressing modes is used to access a memory operand. PC has a current
value of
ECE 662 Midterm 2 - Solutions
Spring 2009
Name_
1. For the OSIAC 662 machine, can the following register transfers be done in one state? If yes,
specify the control lines activated for achieving the transfer. If not decompose the register
transfer to mult
ECE5362 Midterm- Solution
Sp 2013
Name_
1. Convert the following pairs of decimal numbers to 11-bit, signed, 2s complement binary
numbers and add them. State whether or not overflow occurs in each case (10 points).
For 11 bits, the range of representation
~ ncfw_
ppxnff0fr0ig
d o d tw n d ncfw_ cfw_ oqw ncfw_ ncfw_
r`ljpnrifpjU0jpnczcptV'p0rh`p00tf|w$Vpw0p0
t n cfw_ oqw n nt w n q t~ w ntw~ q d cfw_ oqw
fc0frlwh0tji0jpw"0i"0rn00jfh0ji0tff|0
pjp0zsrlfrljmcj00cr$jf2v0|Fg 0r"f0q0t
n nt w w~ o o tw n g
ECE662 (Sp 2012) Machine Problem 2
Due Wednesday, May 30, 2012
This is the second machine problem of this course. You can choose one partner to work together for writing
microinstructions to implement SUB and NEG for all the addressing modes. The HALT mus
*
* This program is developed for *
* testing Machine Problem 2 *
* Spring 2007 by Y.F. Zheng *
*
start test1
D009 AC
000D X (memory location)
000E SP (memory location)
0000 PC
0000 CVZN
5000 OR AC, AC
5011 OR AC, (X)
5012 OR AC, (SP)
5021 OR AC, (X)+
502
Description for the OSIAC 662
(Developed by Prof. Chuck Klein and modied for ECE 662 Spring 2012)
All words are 16 bits long with the least signicant bit labeled 0 and the most
signicant labeled bit 15.
This machine has four general purpose registers alth
p g r X H b t B bd xz~ p BC f r9ICeXibfseBbGp( GedQBeHbl yef(sHGnf99Y G(9Y 9$vvgd yenf QzQBsHDbIr9QoDHGsubGedYerabGwvqQ$If9oDXYDbQHGederqQpsHQCGedsDH$d X B r b r H b tC XE T bp g Xp r r F H b tC b bp g H b B b eQreHSQQgSe9sCGGed(iBeHbh9ICeXQSICcDiP&gsripe
8:00am MWF, 0004 Scott Lab., Spring 2013
Course Instructor: Prof. Yuan F. Zheng
Announcements:
Machine Problem #1 (See below) is assigned and is due in class on Wednesday,
February 20.
Homework #4 (see below) is assigned and is due in class on Monday, F
The Ohio State University
Department of Electrical and Computer Engineering
ECE 662
Theory and Design of Digital Computers
2005
Autumn
Meeting Time: 12:30 pm MWF, 220 SB
Instructor: Professor Yuan F. Zheng
Office: 720 Dreese Lab
Office Hours:
1:30-2:30 pm
The Ohio State University
Department of Electrical and Computer Engineering
ECE 662
Theory and Design of Digital Computers
2009
Autumn
Meeting Time: 2:30 pm MWF, 0277 CL
Instructor: Professor Yuan F. Zheng
Office: 720 Dreese Lab
Office Hours:
1:30-2:30 pm
ECE662 (Sp 2008) Machine Problem 2
Due May 16, 2008
This is the second machine problem of this course. You can choose a partner to work together for writing
microinstructions to implement AND and INC for all the addressing modes. The HALT must also work.
ECE662 (Sp 2007) Machine Problem 2
Due May 18, 2007
This is the second machine problem of this course. You can choose a partner to work together for writing
microinstructions to implement OR and NEG for all the addressing modes. The HALT must also work. T
ECE662 (Au 2010) Machine Problem 2
Due Wednesday, November 17, 2010
This is the second machine problem of this course. You can choose a partner to work together for writing
microinstructions to implement SUB and NEG for all the addressing modes. The HALT
ECE662 (Au 2005) Machine Problem 2
Due November 14, 2005
This is the second machine problem of this course. You can choose a partner to work together for writing
microinstructions to implement AND and INC for all the addressing modes. The HALT must also w
| m h hz gm z m d k h p h dz d k d
e9ihb9ox9ijobcfw_ae99xji8omhxfgenmji999ef9ionmi9fem
| | d k m u d d km h m km m |
j9eomhPhcfw_f9ihefmdomonm9o%jfomfe9ji~Ede)ifhjoP9i
g gm z | h u mu | |z | | gm g |m
#oeRffd4fme|i|apdoq'9j9ih9ei9xf9xeT#9iye
)fP9fiX
ECE5362 (Sp 2013) Machine Problem 1
Due February 20, 2013
This is the first machine problem of this course. You will run the register transfers needed to do the fetch cycle, and
execution cycles for two instructions: ADD AC,AC and HALT. You will try this
ECE 5362 Homework 5 Solution
1.
Solution:
a. Red parts below are to be added to the original state machine from Lecture #18.
State
0
1
Register Transfer
[PC] MAR
[MAR] MDR
Control Lines
OPC, IMAR
Read, Inhibit if not MFC
2
3
4
[MDR] IR
[PC]+1 Q
[Q] PC
OMD
ECE 5362 Homework 5
Hard Copy Due 10:20am Oct 16, 2017
1. (70 pts) Implement two additional instructions for the Example Control Unit (Simplified OSIAC
5362). Start with the version in the Lecture Note, where we have already implemented three
instructions
ECE 5362 Homework 4 Solution
1. (3pts each = 33pts)
Solutions:
a. rac=1 rn=2 ib p1 oadder
b. rac=1 rn=3 it2
c. Cannot be done. [PC]+1 has to go to Q first.
d. ot5 ib comp p1 oa oadder
e. Cannot be done. 2s complement must be done on the B side of the adde
ECE 5362 Homework 4
Hard Copy Due 10:20am Oct. 9, 2017
1. (33 pts) The following question is related to the OSIAC machine. For each of the
following operations, either list the control lines to make all the register transfers happen
in a single clock cycl
ECE5362 Midterm 1
Sp 2017
Name_
1.
Mark (give) the correct answers for the following multiple choice questions (10 points).
a. In the computer, the ALU can do subtraction as well as addition by changing the
electronic circuits from Addition to Subtraction