ECE 3561
Homework 3 Solutions
Autumn 2013
Due Date: September 23, 2013
1. Excitation Equations:
JA = X
KA = QC
TB = QA
State/Output Table:
P.S.
QA QB QC
a
0
0
0
a
0
0
0
b
0
0
1
b
0
0
1
c
0
1
0
c
0
1
0
ECE 3561
Homework 3 Assignment
Autumn 2013
Due Date: September 23, 2013
For the questions below, please use the timing data available on Carmen.
1. Analyze the clocked synchronous state machine in Fig
ECE 3561
Homework 4 Assignment
Autumn 2013
Due Date: September 30, 2013
For the questions below, please use the timing data available on Carmen.
1. A microprocessor has an 8-bit address bus (A7, A6, .
ECE 3561
Name: _
Fall 2012
Quiz 2
Write a VHDL ENTITY and
ARCHITECTURE for a half adder.
A block diagram of the half adder is shown
to the right. A and Cin are inputs. Sum and
Cout are the outputs wit
Due: 03/24/2017
ECE 3561 Project 2: Using VHDL to Design a Simple Sequential Machine
Project 2: Using VHDL to Design a
Simple Sequential Machine
In this project, you will use VHDL to design the circui
ECE 3561
Advanced Digital Design
Autumn 2013
The Ohio State University
Department of Electrical and Computer Engineering
ECE 3561
Advanced Digital Design
Meeting Time:
Instructor:
Ofce:
Ofce Hours:
Co
ECE 3561
Homework 4 Assignment
Spring 2013
Due Date: February 13, 2013
For the questions below, please use the timing data available on Carmen.
1. What is the counting sequence of the circuit shown in
ECE 3561
Sample Midterm Exam Questions
Spring 2013
1. Simple Circuit Analysis
Analyze the following circuit using the three step approach.
POC
CLR
JA
KA
QA
QA
QA
CLK
POC
JB
CLR
KB
QB
QB
QB
(a) Provide
ECE 3561
Midterm Exam 2 Solutions
Spring 2013
1. State Elimination and Circuit Equivalence (5pt. + 15pt. + 5pt. + 10pt.)
Consider the following state machines (Circuits N1 and N2 ).
X
Z
X
Z
A
X
X
Z
B
ECE 3561
Sample Midterm Exam Questions
Autumn 2013
1. Simple Circuit Analysis
Analyze the following circuit using the three step approach.
POC
CLR
JA
KA
QA
QA
QA
CLK
POC
JB
CLR
KB
QB
QB
QB
(a) Provide
Due: 03/18/2013
ECE 3561 Project 2: Using VHDL to Design a Simple Sequential Machine
Project 2: Using VHDL to Design a
Simple Sequential Machine
Instructor Prof. Eylem Ekici
In this project, you will
ECE 3561
Homework 4 Assignment
Spring 2016
Due Date: February 22, 2016
For the questions below, please use the timing data available on Carmen.
1. A microprocessor has an 8-bit address bus (A7, A6, .
ECE 3561
Midterm Exam 1 Solutions
Spring 2013
1. Simple Circuit Analysis (20pt. + 15pt.)
Analyze the following circuit using the three step approach.
X
J1
Q1
K1
Q1
T 0 Q0
Q
0
CLK
(a) Provide 1) equati
ECE 3561
Homework 5 Assignment
Spring 2013
Due Date: February 25, 2013
1. Draw the state diagram for a clocked synchronous state machine with two inputs, INIT and X, and
one Moore-type output Z. As lo
ECE 3040, Fall 2016
Homework 6
Due by Oct. 26th
1. A 38kW 440V three-phase 60-Hz six-pole wye-connected induction motor has the following
parameters per phase, with the magnetizing current ignored:
R1
ECE 3561
Project 3 Assignment
Spring 2017
Due Date: April 17, 2017
This project will be completed entirely on your own. If you need to consult with other members,
please write down their names in the
Lecture 4.3: Sequential circuit
analysis
Advanced digital circuits
Jian Tan
ECE 3561
Spring 2016
Review: MSI counter design
Design a circuit using a 74LS163 and at most 3
NAND gates to count the fo
Lecture 4.1: Design Counters
Advanced digital circuits
Jian Tan
ECE 3561
Spring 2017
1
Modulo-8 counter using T FF
A ring of transitions: 0->1->2->3->4->5->6->7->0->
How many FFs are needed?
N=log8 (
Lecture 1: Introduction
Advanced digital circuits
Jian Tan
ECE 3561
Spring 2017
Why this course?
Form background for other classes in computer engineering:
VLSI Design, FPGA Design, Computer Archite
ECE 3561
Midterm Exam Practice Questions
Spring 2017
1. HW assignments 11.2, 11.13, 11.15,
2. Latches and Flip-flops
A latch is designed in the following figure (1), using two switches that are contro
Lecture 1.2: Latches
one bit of memory
Advanced digital circuits
Jian Tan
ECE 3561
Spring 2017
Recall: Feedback on two inverters
Memory (= state)
0
X
Y
X
NOT X
0
1
1
0
1
Z=X
X
Y
Z=X
two states!
We wi
ECE 3561 Frequently Asked Questions
Q: How do I download and install ISE on windows
A: First, you must download the .tar file from the Xilinx website for the
appropriate OS. In order to unzip it,
ECE 3040, Fall 2016
Homework 5
Due by Oct. 7th
1. For an induction motor, determine the number of poles, the slip, and the frequency of the rotor
currents at the following conditions:
Operation Mode
E
ECE 3561 EXAM 2 SP 2016 Due Friday April 29, 2016 at 5pm
-1-
NAME: _
THIS IS AN Take Home EXAM. As such you have access to reference material,
electronic textbook/notes OK. Help from anyone, except th
ECE 3040 Fall
Homework 2
Due by Sept. 16th
1. A Y-load and a -load are connected in parallel as in shown. Line voltage magnitude at the
source is 208 V.
a. Find the phase voltages at the load 1.
b. Fi
ECE 3040, Fall 2016
Homework 3
Due by Sept 23rd
1.
2. A 80/240V, 3kVA transformer is reconnected as an autotransformer to supply a load at 320,
from a voltage source of 80V.
a. Draw the equivalent cir
ECE 3561 Homework 9 Assignment Autumn 2017
Due Date: December 4, 2017
1. State Machine Design For the state diagram given above, determine the stateioutput table and the
excitation and output func
Read textbook
p.g. 298 - 322
p.g. 591- 593
Project 2 due on Nov. 1st
Lecture 8.1: Introduction to VHDL
Advanced digital circuits
Jian Tan
ECE 3561
Autumn 2017
1
History
Very High Speed Integrated Cir
Review
Theoretical SR Latch State Diagram
SR = 00, 10
SR = 00, 01
SR=(1,1) not
allowed in normal
mode
SR = 1 0
QP
01
SR = 0 1
SR = 0 1
SR = 1 0
QP
10
SR = 11
SR = 1 1
SR = 1 1
QP
00
SR = 0 1
Q=P
SR =
Question: Xilinx always crashes when opening a project with 64 bit
Xilinx navigator on Windows 10. The following solution is from
https:/www.xilinx.com/support/answers/62380.html.
1. Go to C: disk
ECE 3561
Homework 3 Solutions
Autumn 2017
Due Date: September 25, 2017
1. Excitation Equations:
JA = X
KA = QC
TB = QA
JC = QB
KC = QB
Z = QB + QC
The following solution is based on the longer table t