ECE 3561
Homework 3 Solutions
Autumn 2013
Due Date: September 23, 2013
1. Excitation Equations:
JA = X
KA = QC
TB = QA
State/Output Table:
P.S.
QA QB QC
a
0
0
0
a
0
0
0
b
0
0
1
b
0
0
1
c
0
1
0
c
0
1
0
d
0
1
1
d
0
1
1
e
1
0
0
e
1
0
0
f
1
0
1
f
1
0
1
g
1
1
ECE 3561
Homework 3 Assignment
Autumn 2013
Due Date: September 23, 2013
For the questions below, please use the timing data available on Carmen.
1. Analyze the clocked synchronous state machine in Figure 1. Write excitation equations, draw the
state table
ECE 3561
Homework 4 Assignment
Autumn 2013
Due Date: September 30, 2013
For the questions below, please use the timing data available on Carmen.
1. A microprocessor has an 8-bit address bus (A7, A6, . , A0). Using these address lines, we want to
control 8
ECE 3561
Name: _
Fall 2012
Quiz 2
Write a VHDL ENTITY and
ARCHITECTURE for a half adder.
A block diagram of the half adder is shown
to the right. A and Cin are inputs. Sum and
Cout are the outputs with
Sum = A xor Cin
Cout = A and Cin
A
Cout
Half
Adder
Us
ECE 3561
Midterm Exam 2 Solutions
Spring 2013
1. State Elimination and Circuit Equivalence (5pt. + 15pt. + 5pt. + 10pt.)
Consider the following state machines (Circuits N1 and N2 ).
X
Z
X
Z
A
X
X
Z
B
a
Z
X
Z
D
X
Z
X
Z
b
Z
1
X
X
X
d
Z
X
C
X
Z
X
Z
c
Z
X
e
Z
ECE 3561
Advanced Digital Design
Autumn 2013
The Ohio State University
Department of Electrical and Computer Engineering
ECE 3561
Advanced Digital Design
Meeting Time:
Instructor:
Ofce:
Ofce Hours:
Course Web Site:
Text Book:
Prerequisites:
Computer Proje
ECE 3561
Sample Midterm Exam Questions
Autumn 2013
1. Simple Circuit Analysis
Analyze the following circuit using the three step approach.
POC
CLR
JA
KA
QA
QA
QA
CLK
POC
JB
CLR
KB
QB
QB
QB
(a) Provide 1) equations, 2) table, and 3) state diagram.
(b) What
ECE 3561
Homework 4 Assignment
Spring 2013
Due Date: February 13, 2013
For the questions below, please use the timing data available on Carmen.
1. What is the counting sequence of the circuit shown in Figure 1?
Note that 74LS169 loads 4 bit data when LD i
ECE 3561
Sample Midterm Exam Questions
Spring 2013
1. Simple Circuit Analysis
Analyze the following circuit using the three step approach.
POC
CLR
JA
KA
QA
QA
QA
CLK
POC
JB
CLR
KB
QB
QB
QB
(a) Provide 1) equations, 2) table, and 3) state diagram.
(b) What
ECE 3561
Homework 4 Assignment
Spring 2016
Due Date: February 22, 2016
For the questions below, please use the timing data available on Carmen.
1. A microprocessor has an 8-bit address bus (A7, A6, . , A0). Using these address lines, we want to
control 8
ECE 3561
Midterm Exam 1 Solutions
Spring 2013
1. Simple Circuit Analysis (20pt. + 15pt.)
Analyze the following circuit using the three step approach.
X
J1
Q1
K1
Q1
T 0 Q0
Q
0
CLK
(a) Provide 1) equations, 2) table, and 3) state diagram. Do not add rows to
ECE 3561
Homework 5 Assignment
Spring 2013
Due Date: February 25, 2013
1. Draw the state diagram for a clocked synchronous state machine with two inputs, INIT and X, and
one Moore-type output Z. As long as INIT is asserted, Z remains 0. Once INIT is negat
L4 An overview of
Quartis
Quartis
Quartis the Altera FPGA design tool
9/2/2012 ECE 3561 Lect
4
Copyright 2012 - Joanne DeGroat, ECE, OSU
Some important points
When creating a project
Avoid reserved words
The project, top VHDL entity, and design name
shoul
L6 Derivation of State
Graphs and Tables
State Graphs and Tables
Problem Statement translation
To State Graphs
To State Tables
Ref: text Unit 14
9/2/2012 ECE 3561 Lect
6
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Derivation of State Graphs
Problem Statem
ECE 3561
Advanced Digital Design
Department of Electrical and
Computer Engineering
The Ohio State University
ECE 3561 - Lecture 1
1
Today
The
Course
Syllabus
Intro
ECE 3561 - Lecture 1
2
Course Philosophy and Objective
Familiarize
students with advanc
L14 VHDL Language
Elements II
VHDL Language Elements
Elements needed for FPGA design
Types
Basic Types
Resolved Types special attributes of resolved types
Concurrent Statements
Sequential Statements
Design Units
Packages
Ref: text Unit 10, 17, 20
9/2/2012
ECE 3561 Frequently Asked Questions
Q: How do I download and install ISE on windows
A: First, you must download the .tar file from the Xilinx website for the
appropriate OS. In order to unzip it, it is likely that you will need a 3rd party
software.
Sequential Design Basics
Lecture 2 topics
A review of devices that hold state
A review of Latches
A review of Flip-Flops
8/22/2012 ECE 3561
Lect 2
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Latches and Flip-Flops
What is the difference?
Flip-flops use a
L9 VHDL Overview
VHDL Overview
Rules for State Assignment
Application of rule
Gate Implementation
Ref: text Unit 15.8
9/2/2012 ECE 3561 Lect
9
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Overview
HDL Hardware Description Language
A language that allows de
L8 Reduction of State
Tables
Reduction of states
Given a state table reduce the number of
states.
Eliminate redundant states
Ref: text Unit 15
9/2/2012 ECE 3561 Lect
7
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Objective
Reduce the number of states in th
L9 State Assignment and
gate implementation
States Assignment
Rules for State Assignment
Application of rule
Gate Implementation
Ref: text Unit 15.8
9/2/2012 ECE 3561 Lect
9
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Rules for State Assignment
Situation:
L5 Sequential Circuit
Design
Sequential Circuit Design
Mealy and Moore
Characteristic Equations
Design Procedure
Example Sequential Problem from
specification to implementation
9/2/2012 ECE 3561 Lect
5
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Types of
L14 VHDL Language
Elements II
VHDL Language Elements
Elements needed for FPGA design
Types
Basic Types
Resolved Types special attributes of resolved types
Concurrent Statements
Sequential Statements
Design Units
Packages
Ref: text Unit 10, 17, 20
9/2/2012
L16 Testbenches for
state machines
VHDL Language Elements
More examples
HDL coding of class examples
Testbench for example
Testing of examples testbench construction
Note trade off and difference in Mealy vs Moore
implementation from simulation results
Co
L7 Derivation of State
Graphs and Tables
Moore Machines
State Graphs and Tables
Problem Statement translation for Moore
Machines
To State Graphs
To State Tables
Ref: text Unit 14
9/2/2012 ECE 3561 Lect
7
Copyright 2012 - Joanne DeGroat, ECE, OSU
2
Deriva
L15 Specification of
State Machines
VHDL State Machines
State Machine Basics
VHDL for sequential elements
VHDL for state machines
Example Tail light controller
Example counter
Example gray code counter
Ref: text Unit 10, 17, 20
9/2/2012 ECE 3561 Lect
9
Co
Due: 03/24/2017
ECE 3561 Project 2: Using VHDL to Design a Simple Sequential Machine
Project 2: Using VHDL to Design a
Simple Sequential Machine
In this project, you will use VHDL to design the circuit in Project 1 that models a
simple sequential machine
ECE 3040, Fall 2016
Homework 4
Due by Sept 30th
1. A three-phase transformer bank is to handle 400kVA and have a 34.5kV/13.8kV voltage ratio.
Find the rating of each individual single-phase transformer in the bank (high voltage, lowvoltage, turns ratio, a
1
ECE 3040 Fall, 2016
Homework 7
Due by Nov. 4nd
1. A synchronous generator with a synchronous reactance of 5 is connected to an infinite bus
which voltage is 4kV, through an equivalent reactance of 1 . The power transfer capacity of
the system is 250 kW.
ECE 3040, Fall 2016
Homework 3
Due by Sept 23rd
1.
2. A 80/240V, 3kVA transformer is reconnected as an autotransformer to supply a load at 320,
from a voltage source of 80V.
a. Draw the equivalent circuit of the reconnected autotransformer. If the winding