ECE5020
Homework 2
Reading and Skimming:
Textbook:
Continue Chp. 1 1.7 - 1.12 Note the various carry circuit examples in the MIPS hardware
descriptions and in problems 1.6c, 1.7d, 1.18, 1.19, 1.20 (3r
ECE5020
Homework 2
Reading and Skimming:
Textbook:
Continue Chp. 1 1.7 - 1.12 Note the various carry circuit examples in the MIPS hardware
descriptions and in problems 1.6c, 1.7d, 1.18, 1.19, 1.20 (3r
ECE5020 Homework 1
Skimming and Reading:
Textbook Chapter 1 (3rd ed. or 4th ed). Use Lecture slides as an abstraction for the
textbook content. Skim/Skip the behavioral models of the MIPS processor (L
ECE 5020
Homework 4
The following is from the online 4th chapter of the 3rd ed. of the textbook.
1. Analyze the problem of an inverter chain driving a large capacitive load, this led to the invention
ECE5020 Some Hmwrk 4 Solutions
2. and 3. Problems 4.10, 4.12 description are in attached pages:
4. Problem using Figure 4.16 (3rd ed.) or Figure 4.29 (4th ed.)
see slide.
a). Change the final load cap
Exam 1 ECE 5020 - Aut 2012
Name _
4. In the AMI05 cell INVZ what was the layout trick to increase speed and how did it
work?
Depends on your definition of a engineering trick vs. a sound engineering a
ECE5020
Homework 1
Chapter 1 Exercises
1.6, 1.9a (1.4, 1.7a 3rd ed.) (comment on a more compact solution vs. the online solution
in terms of timing delay)
1.15 (1.13 3rd ed) try and draw the schematic
ECE5020
Homework 3 Some Solutions
1.Explain how a load line is plotted on a NMOS inverter curve and use this to explain
the IV curves of a CMOS inverter.
Shown in class.
2. Modify the CMOS gate exampl
ECE5020
Homework 3
Writing
1. Explain how a load line is plotted on a NMOS inverter curve and use this to explain
the IV curves of a CMOS inverter.
2. Modify the CMOS gate example in topspice with a D
ECE5020
Homework 4 Solutions.
Weste/Harris Chp. 4 3rd ed.
Problems 4.10, 4.12
See attached.
3. Problem using Figure 4.16:
a). Change the final load capacitance from 20 to 72. Calculate f and delay D.
Lecture 0:
Introduction
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low
Fall 2017 EECE 5644 Homework #1
Reading: Appendices A.1 A.5, Notes, Chapter 2.12.7
1.1 (10 pts) Let x be a real-valued random variable.
(a) Prove that the variance of x = 2 = E[(x )2 ] = E[x2 ] 2 .
(b
EECE 5639: Computer Vision I
Homework 1
Given September 12, 2017; Due: September 19, 2017
1. Consider an ideal pinhole camera with its center of projection located at the origin of the world
coordinat
ECE5020
Homework 4
Skimming and Reading:
Weste/Harris 3rd ed. textbook:
-Logic Effort Slides and related material from Chp. 4 (3rd ed. on Carmen)
-Weste/Harris Simulation slides and Cadence tutorial o
ECE5020
Homework 3
Skimming and Reading:
Harris textbook:
Carmen.
Logic Effort Slides and related material from Chp. 4 (3rd ed. on
Writing:
1.From the AMI 0.5um Design Library. Change the widths for e
ECE5020
Homework 1
Skimming and Reading:
Harris Textbook Chapter 1. Use Lecture slides as an abstraction/skimming guide for the
textbook content. Harris webpage: Lecture 0, Lecture 1, Lecture 2
Rabaey
ECE5020
Homework 2
Reading and Skimming:
Textbook:
Continue Weste Chp. 1 1.7 - 1.12 Note the various carry circuit examples in the MIPS
hardware descriptions and in problems 1.6c, 1.7d, 1.18, 1.19, 1.
ECE5020
Homework 1
Solutions:
Harris Chapter 1 Exercises
1.6, 1.9a (comment on a more compact solution vs. the online solution in terms of
timing delay)
1.15 try and draw the schematic to be similar t
ECE5020
Homework 1
Skimming and Reading:
Textbook Chapter 1 (3rd ed. or 4th ed). Use Lecture slides as an abstraction/skimming
guide for the textbook content.
D. Harris webpage: Lecture 0, Lecture 1,
ECE5020
Homework 3
Reading
Mos transistor chapter of the textbook and related slides. Use Chp. 4 as a lookahead on
DC and transient response to develop abstracted transistor models from Chp. 2.
Writin
Winter 14 AMS225 Homework 1 Solution
1. Since X = (X1 , X2 , X3 )T is 3-variate Normal, its subsets are also multivariate Normal. Thus,
it suffices to check that the cross-covariance matrix of any two
Electronic Materials
Syllabus
Summer I 2017
EECE3392 Electronic Materials SUMMER I 2017
Credits: 4 SH
Instructor:
Vincent G Harris
University Distinguished Professor
William Lincoln Smith Professor
El
In particular, the Logical Effort Slides, preceded by the DC and Transient Response Slides.
Logical Effort and analysis for optimum number of Stages, Log4F and branching
Tau scaling across process nod
ECE 5020
Mixed Signal VLSI
Lecture 1
Intro
Prof. Waleed Khalil
[email protected]
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
1
Course Outline
Introduction: Issues in di
ECE 5020
Mixed Signal VLSI
Lecture 5
IC Manufacturing Process
Prof. Waleed Khalil
[email protected]
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
1
Feature Size
The Feat
ECE 5020
Mixed Signal VLSI
Lecture 3
MOS Transistor
Prof. Waleed Khalil
[email protected]
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
1
The Diode
B
A
Al
SiO2
p
n
Cross
ECE 5020
Mixed Signal VLSI
Lecture 7
Pass Transistor Logic
Prof. Waleed Khalil
[email protected]
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
1
Pass-Transistor Logic (PT