ECE 561 (Sp 2010) Homework #2 Solutions
1. Problem 8.13. The counting direction is controlled by QD: count up when QD=1, count down when QD=0. A load occurs when the counter is in the terminal state: 1111 when counting up, 0000 when counting down. The MSB
ECE561: Digital Circuit Design
Sp 2010 Homework #2 1. Problem 8.13. Note that 74x169 loads 4 bit data when LD is asserted. If LD is negated and both of ENP and ENT are asserted, 74x169 counts up when UP/DN is 1 and counts down when UP/DN is 0. RCO has the
Due Wed. Oct 19
E CE265
H omework # 3 A u 11
A ssemble t his c ode: i nstructions, a ddressing m odes, a nd a ssembler d irectives
*1
Show memory contents o f a ssembled code and data. A lso s how c ontents o f symbol table.
org
$ 50
s tart
n op
nop
bne
s
ECE 561
Homework #3
Autumn 2011
Due on November 2, 2011
Problems:
1. (a) Use the 9step design approach to design a 2bit version of the 74LS194 with NAND gates
(LS00, LS10, . . . ), inverters (LS04), and D ip/ops (74LS74). You need not provide a
state di
ECE561: Digital Circuit Design
Winter 2012
Homework #2
1. Design a modulo64 counter with CLR_L input that counts from 0 to 63 using two 74x163s
and one 74x139. Use logic gates if necessary, but the number of gates must be minimal.
2. Problem 8.13 (show t
ECE 561
Homework #3 Partial Solution
Autumn 2011
1. Problem 7.44.
State Diagram:
X
INIT
INIT X
a
X
b
X
INIT X
X
d
X
X
f
c
X
g
X
X
e
X
X
X
INIT
Z
h
INIT
2. Problem 7.46.
Equations:
D1 = Q2 X + Q1 Q2 X
D2 = X + Q1 Q2 + Q1 Q2
Z = Q1 Q2
3. Problem 7.60.
Compa
ECE 561
Homework #4
Autumn 2011
Due on November 14, 2011
Problems:
Use the VHDL editor in Xilinx to verify the correctness of your syntax for each of the following VHDL programs.
Include the Xilinx compile report of each VHDL program in your results.
1. P
ECE 561
Homework #4 Solutions
Autumn 2011
1. Sevensegment decoder
library IEEE; use IEEE.std_logic_1164.all;
entity V74x49b is
port (
D: in STD_LOGIC;
C: in STD_LOGIC;
B: in STD_LOGIC;
A: in STD_LOGIC;
BI_L: in STD_LOGIC;
ENHEX, ERRDET: in STD_LOGIC;
S_L
ECE 561
Homework #2 Solutions
Autumn 2011
1. Problem 8.13.
The counting direction is controlled by QD: count up when QD=1, count down when QD=0.
A load occurs when the counter is in the terminal state: 1111 when counting up, 0000 when
counting down. The M
ECE 561
Homework #2
Autumn 2011
Due on October 17, 2011
Problems:
1. Problem 8.13. Note that 74x169 loads 4 bit data when LD is asserted. If LD is negated and
both of ENP and ENT are asserted, 74x169 counts up when UP/DN is 1 and counts down
when UP/DN is
ECE 561
Homework #1 Solutions
Autumn 2011
1. Problem 7.8
Hook up S L and R L to the PR and CLR inputs, respectively. Ground CLK and D or
Connect Q to D and let CLK run from an output source.
2. Problem 7.17
P.S.
A
B
C
D
E
F
G
H
Z1
1
1
0
0
0
0
1
1
N.S. for
ECE 561
Final Study Guide
Autumn 2011
1. The VHDL code for the following entity named SIMPLE is to be written. Fill in the blank
parts in the following VHDL program. The resulting program should work.
X=1
X
SIMPLE
Y
CLK
A
B
1
0
X=0
library IEEE;
use IEEE.
ECE 561
Final Study Guide Solution
1.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity simple is
Port ( CLK : in std_logic;
X : in std_logic;
Y : out std_logic);
end simple;
architecture simple_a of simple is
type state_type is (A, B);
signal mystate: st
ECE 561
Homework #5
Autumn 2011
Due on November 28, 2011
Problem:
Construct a clocked sequential circuit that will turn on a light (LIGHT) as the rst person enters a
room, and turn off the light as the last person leaves. Assume that there is a single doo
ECE 561
Homework #5 Solution
Autumn 2011
The state diagram is designed as follow:
Three states are needed to keep count of the number of persons in the room:
a 0 persons
c 1 person
e 2 persons
The other states are transition states to realize the correc
ECE 561
Midterm Study Guide
Autumn 2011
1. Analyze the following circuit by providing a complete state diagram for it. Note that PR
and CLR for the 74LS74A are asynchronous. Also, note that the input POC is lowactive.
The output GO is highactive.
+5V
P
2
Introduction:
In this project we gained familiarity with the Xilinx 9.1 software for use in logic design. We analyzed
a given circuit, determined how to optimize it, and implemented the design in Xilinx. We then
simulated it.
Design:
We analyzed the giv
ECE 561
Homework #3
Spring 2009
Due on April 6, 2009
Problems:
1. (a) Use the 9step design approach to design a 2bit version of the 74LS194 with NAND gates
(LS00, LS10, . . . ), inverters (LS04), and D ip/ops (74LS74). You need not provide a
state diagr
ECE 561
Homework #4
Spring 2009
Due on May 22, 2009
Problems:
Use the VHDL editor in Xilinx to verify the correctness of your syntax for each of the following VHDL programs.
Include the Xilinx compile report of each VHDL program in your results.
1. Proble

library IEEE;
use IEEE.std_logic_1164.all;
entity smexamp is
port ( CLOCK, A, B: in STD_LOGIC;
RESET: in STD_LOGIC;
Z: out STD_LOGIC );
end;
architecture smexamp_arch of smexamp is
type State_type is (INIT, A0, A1, OK0, OK1);
signal Sreg, Snext: Sta