Department of Electrical and Computer Engineering
Spring 2012
TuTh 3:30-4:50
Bang-Sup Song
ECE264B
Home Work #2 (Due: April 24, 2012)
The small-signal circuit of a two-stage Miller compensated opamp is shown below. Note that
only important devices are mar
Department of Electrical and Computer Engineering
Spring 2012
TuTh 3:30-4:50
Bang-Sup Song
ECE264B
Home Work #1 (Due: April 12, 2012)
In the following wideband trans-resistance amplifier, assume that all transistors are sized to
be 100/0.18 and biased to
UNIVERSITY OF CALIFORNIA, SAN DIEGO
Department of Electrical and Computer Engineering
Bang-Sup Song
ECE264B
Winter 2012
TuTh 3:30-4:50
CMOS ANALOG INTEGRATED CIRCUITS AND SYSTEMS II
This course is the continuation of ECE264A and the second one of the four
Advanced Analog Integrated Circuit
Term Project
by Tai-Cheng Lee
Due: June 28, 2010 (Presentation will be held on June 29)
In this project, a 10-bit 20 Msamples/sec pipelined analog-to-digital converter (ADC) needs to be
designed. The technology le, CIC c
Advanced Analog Integrated Circuit
Term Project
by Tai-Cheng Lee
Due: June 28, 2010 (Presentation will be held on June 29)
In this project, a 10-bit 20 Msamples/sec pipelined analog-to-digital converter (ADC) needs to be
designed. The technology le, CIC c
AAIC Homework 2
Due Tue Apr. 20, 2010
by Tai-Cheng Lee
Please use course transistor model for your simulation.
1. In this problem, we study the effect of a nonideal voltage reference upon the settling behavior of a
6-bit segmented DAC. The circuit is show
*AAIC 2010 device models
* level 1 mos models for ldrawn =0.3u
* note: for a device w microns wide, the source/drain junction area
* as = ad = 0.6*w micron*2 and the perimeter ps = pd = 2*w+1.2 microns.
* the value of lambda is linearly proportional
Homework 1
Due Tue. Mar. 30, 2010
by Tai-Cheng Lee
Please download the .LIB from course webpage.
1. For the following sampling circuit, where Ron =300, and CH =1 pF. The circuit has been designed for a
12-bit system.
(a) Suppose Vout (t = 0) = 0 and Vin i
Advanced Analog Integrated Circuit Design
Term Project
by Tai-Cheng Lee
Due: June 22, 2009
In this project, an 8-bit cyclic analog-to-digital converter (ADC) needs to be designed. The technology le, CIC cyber shuttle 0.18-m, can be obtained from your own
1.
(a)
For a differential pair, we need
difference to switch
is the overdrive voltage of M1/M2 when
completely, where
they have the same current.
Thus,
.
.
.
.
(b)
Since both the current source
and differential pair M1/
M2 work in saturation region, the
HW2 Read Me
By TA Chia-Chi, Ho
Download the .vec file from the course
website or
website, or
http:/homepage.ntu.edu.tw/~r97943111/AAI
C/Digital_Input.rar
Extract the files to the same directory as
your spice files, such as .sp files.
input_ramp.vec is
AAIC Homework 2
Due Tue. Apr. 13, 2009
by Tai-Cheng Lee
Please use the course SPICE device model for your simulation.
1. The following gure shows a 6-bit current-steering CMOS DAC, where RL = 50 and IB = 156.25A.
The circuit consists of 64 nominally ident
1.
(a)
(b)
Since
while SDR = 50dB,
(c)
,
. Therefore,
.
;
The left one is the 3rd harmonic tone reflected.
(d)
They all have similar spectrums. Skirt effect occurs.
2.
(a)
.
.
(b)
The sample curve for each input frequency are shown as the figure
below,
A
Homework 1
Due Tue. Mar. 24, 2009
by Tai-Cheng Lee
1. In this problem, we would like to use MATLAB to perform spectrum simulation. Please perform 1024-pt
FFT for the following setups.
(a) fsample = 1M Hz and fin = 11/1024M Hz . Then, add the white Gaussia
Oversampled Data Converter
Tai-Cheng Lee
Nyquist-Rate A/D Converters
Can be roughly divided into three categories
Low to medium speed,
high accuracy
Medium speed,
medium accuracy
Integrating
Oversampling
Oversampling
Successive approximation
Algorithmic
H
Analog-to-Digital Converter
Case Study
Case Study
1
Tai-Cheng Lee
Spring 2007
An 8-b 100-MSample/s CMOS Pipelined Folding ADC
The concept of the two-stage and folding ADC:
2
Tai-Cheng Lee
Spring 2007
An 8-b 100-MSample/s CMOS Pipelined Folding ADC
Flash