Fall 2008
ECE608, Homework #10 Solution
Tuesday, December 9, 2008
(1) CLR 22.1-6
We are looking for a universal sink i.e., a vertex with in degree of |V | 1 and out
degree of zero. In the adjacency matrix the elements in row i represent the edges that
our
Fall 2010
ECE608, Homework #12 Solution
(1) CLR 34.1-1
(a) If Longest-Path P, then we can come up with an algorithm Longest-PathLength(G, u, v ).
Longest-Path-Length(G, u, v )
1. for k = |V | 1 to 1
2.
do Ans = Longest-Path(G, u, v, k )
3.
if (Ans = yes)
ECE608, Homework #11 Solution
(1) CLR 24.1-3
The proof of Lemma 24.2 shows that for every v , d[v ] has attained its nal value after
length (any shortest-weight path to v ) iterations of Bellman-Ford. Thus after m
passes, Bellman-Ford can terminate. We do
ECE608, Homework #11
(1) CLR 24.1-3 The algorithm is not told m, but must terminate even so in m + 1 passes.
(2) CLR 24.1-4
(3) CLR 24.2-4
(4) CLR 24.3-2
(5) CLR 24.3-10
(6) CLR 24-2
(7) CLR 25.1-9
(8) CLR 25.2-6
(9) CLR 25.2-7
(10) CLR 25-1
1
ECE608, Homework #9 Solution
(1) CLR 16.1-3
Let S be the set of n activities. The obvious solution of using Greedy-ActivitySelector to nd a maximum-size set S 1 of compatible activities from S for the rst
lecture hall, then using it again to nd a maximum-
ECE608 Homework #7 Solution
(1) CLR 11.1-1
To nd the maximum element of the set S , it requires searching the entire table T
in the worst case. Note that NIL is returned if there are no elements in the table T ;
otherwise, the index to the largest element
ECE608 Homework #6 Solution
(1) CLR 8.1-3
If the sort runs in linear time for m input permutations, then the height h of those
paths of the decision tree consisting of the m corresponding leaves and their ancestors
must be linear. Hence, we can use the sa
ECE608 Homework #5 Solution
(1) CLR 6.1-6
No, 23, 17, 14, 6, 13, 10, 1, 5, 7, 12 is not a heap because the heap property does not
hold between the 4th element and its second child, the 9th element (i.e., 6 < 7).
(2) CLR 6.1-7
Let i represent the index of
ECE608 Homework #4 Solution
(1) CLR 5.1-3
Perform two calls to BIASED-RANDOM obtaining two bits. The following outcomes
are possible with the shown probability:
1) 1 and 0 with probability = p(1 p)
2) 0 and 1 with probability = p(1 p)
3) 1 and 1 with prob
ECE608, Homework #3 Solution
(1) CLR 4.3-9
T (n) = 3T ( n) + lg n.
Change variables to m = lg n n = 2m .
T (2m ) = 3T (2m/2 ) + m.
Change functions to S (m) = T (2m ).
S (m) = 3S ( m ) + m.
2
This is solvable by case 1 on the Master Theorem, since a = 3,
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Fall 2011
ECE 565, Fall 2011
1
This Unit: Shared Memory Multiprocessors
Application
Three issues
OS
Compiler
CPU
Firmware
I/O
Memory
Digital Circuits
Cache coherence
Synchronization
Memory consist
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Fall 2011
ECE 565, Fall 2011
1
This Unit: Multithreading (MT)
Application
Why multithreading (MT)?
OS
Compiler
CPU
Firmware
Utilization vs. performance
Three implementations
Coarse-grained MT
Fin
ECE565: Computer
Architecture
Instructor: Vijay Pai
Fall 2011
ECE 565, Fall 2011
1
This Unit: Main Memory
Application
OS
Compiler
CPU
Firmware
Memory hierarchy review
Virtual memory
Address translation and page tables
Virtual memorys impact on caches
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Fall 2011
Course administration: via Blackboard
ECE 565, Fall 2011
1
This Unit: Data/Thread Level Parallelism
Application
Data-level parallelism
OS
Compiler
CPU
Firmware
I/O
Memory
Digital Circuits
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Fall 2011
ECE 565, Fall 2011
1
This Unit: Dynamic Scheduling II
Application
Previously: dynamic scheduling
OS
Compiler
CPU
Firmware
I/O
Memory
Digital Circuits
Gates & Transistors
Insn buffer + sche
The Problem With In-Order Pipelines
addf f0,f1,f2
mulf f2,f3,f2
subf f0,f1,f4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
F D E+ E+ E+ W
F D d* d* E* E* E* E* E* W
F p* p* D E+ E+ E+ W
Whats happening in cycle 4?
mulf stalls due to RAW hazard
OK, this is a
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Fall 2011
Course administration: via Blackboard
ECE 565, Fall 2011
1
Lots of Parallelism
Last unit: pipeline-level parallelism
Work on execute of one instruction in parallel with decode of next
Ne
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Lecture TA: None
Fall 2011
Course administration: via Blackboard
Acknowledgements and Disclaimer
Slides developed by Amir Roth of University of Pennsylvania
with sources that included University of
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Fall 2011
Acknowledgements and
Disclaimer
Slides developed by Amir Roth of University
of Pennsylvania with sources that included
University of Wisconsin slides by Mark Hill,
Guri Sohi, Jim Smith, and
ECE565: Computer
Architecture
Instructor: Vijay S. Pai
Lecture TA: None
Fall 2011
Course administration: via Blackboard
Acknowledgements and
Disclaimer
Slides developed by Amir Roth of University
of Pennsylvania with sources that included
University of W
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8
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