EE456 HW9-SOLUTIONS
Problem 1
a-) Block diagram:
Solution Strategy: We need to be able to switch between serial-in and parallel-in, we need a chain of flip flops to store the serial information. For p
EE456 HW9
Due: April 9th 2009
ECE456 HW9
Note: This HW has double the weight of a standard HW. Problem 1 In this homework you will be designing a 4-bit shift register for an on-chip network interface
Random Access Memory
BL
BL
WL
VDD
You can read/write
at comparable speed
Q
Q
Six transistor CMOS RAM
Read Operation
active word line
BL , BL are precharged to VDD
eq ckt :
(Q = 1)
BL
BL
WL
VDD
Q=0
min
EE456 HW-10 SOLUTIONS Theory:
i.) Using the given relations for propagate and generate signals we could write:
For generate:
ii.)
Propagate i:j ( Pi:j) is the collective propagate signal of the bits j
Consider it for a 1-bit adder and verify
Propagate = Does an incoming carry propagate to the next stage? Generate = Do the given inputs create a carry in this stage ?
Generalizing the concept of singl
A Family of Adders
Simon Knowles Element 14, Aztec Centre, Bristol, UK [email protected]
have minimum logical depth like Ladner & Fischers adder, but which express different trade-offs between area an
A Taxonomy of Parallel Prefix Networks
David Harris Harvey Mudd College / Sun Microsystems Laboratories 301 E. Twelfth St. Claremont, CA 9171 1 David [email protected]
- Parallel prefu networks are widel
EE456 HW10
Due: April 30th 2009
EE456 HW-10
(Note: This HW has triple weight + additional bonuses) In this homework, you are going to design a 16-bit pipelined Kogge-Stone adder to be used in the accu
ECE456 HW8
Due date: March. 26th
EE456 HW8
Problem 1. Consider the four-input NAND gate below, where the internal capacitance equals 2 fF, the load capacitance is 24fF, and the top three transistors (
Homework 7 ECE456 Note: This assignment has higher weight than previous assignments.
Due: March 12th
Problem 1: Implement the function below (both the function and its complement) in DCVSL (see page 2
Homework 5
ECE456
Due: March 10
Problem 1: Implement the function below (both the function and its complement) in DCVSL (see page 267 of your textbook). Assume A, B, C, D and their complements are ava
EE456 Lab Tutorial 1
EE456 Lab Tutorial 1
Cadence Virtuoso Schematic Composer Introduction
1.0 Introduction
The purpose of the first lab tutorial is to help you become familiar with the schematic
edit
EE456 Lab Tutorial 2
EE456 Lab Tutorial 2
Cadence HSPICE Simulation Introduction
1.0 Introduction
The purpose of the second lab tutorial is to help you in simulating your inverter design
that you desi
Electromigration
Long-term reliability problem
If in VDD and GND path current is more than 1mA/um width over the line metal
ions move increase resistance eventually open ckts.
This problem does not e
Interconnect:
Capacitive Crosstalk
important for high impedance nodes
X
Vy =
Cxy
Cxy
Vx
Cy + Cxy
Vx
Y
Cy
but usually line y is driven with a finite resistance R
X
Cxy
R
Y
Cy
In the case rise/fall ti
Implementing Strategies for Digital ICs
take advantage of some predesigned modules ( shorten
the design time)
Dig. Implementation
Semi Custom
Block such as INV,
AND/NAND, OR/NOR,
XOR.XNOR, MVX,
ADDER
Dynamic CMOS design
uses N+2 transistors bit no static power
VDD
Clk=0 out=VDD precharge state
as PMOS=on. NMOS=off
Clk
out
A
B
C
Clk=1 out f(A,B,C,D) evaluation state
as PMOS=off. NMOS =on
During Clk
Power consumption in CMOS inverters
*Dynamic power
VDD
CL
Assume zero rise and fall time
VDD
EVDD = C LVDD
EC =
CL
C LVDD
2
2
energy stored in CL
2
energy consumed in PMOS
independent of Rtransisto
Interconnects
Assume 3 line : divide them into equal sections
high resistance
small capacitance
high inductance
high impedance line
(inductive)
high capacitance
small resistance
small inductance
low
Dynamic Behavior (determined by various capacitors)
Overlap capacitance
xd
xd
xd
xd
VD
n+
G
n+
CGSO = CGDO = CoxXdW = CoW
L
S
W
D
Ld
Co = Cgso = Cgdo
Channel Capacitance
G
S
D
n+
G
S
n+
n+
D
n+
B
resi
Devices
Semiconductor Physics review
Diode
MOS transistor
Semiconductor Physics
Charge carriers in semiconductors : electrons, holes
Why do we consider holes?
In metals, there are so many electrons th
Power Consumption
Ppeak, peak power is important for supply line sizing
Ppeak = ipeak Vsupply = max[P(+)]
T
T
Vsupply
Pav = 1/T P(t )dt =
isupply(t)dt
T
0
0
P(t) : instantaneous power
Power consumpti
Chapter 1. Introduction
Read Section 1.1(Historic) + 1.2(Cost) +1.3 (Quality Metrics)
So far you have been introduced to logic design(concept of 0s and 1s). Some of you
know about electronic devices (