1
Chapter 10 Problem Set
Chapter 10 PROBLEMS
1. [C, None, 9.2] For the circuit in Figure 0.1, assume a unit delay through the Register and Logic blocks (i.e., tR = tL = 1). Assume that the registers, which are positive edge-triggered, have a set-up
CHAPTER
5
THE CMOS INVERTER
Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design
5.1 5.2 5.3
Exercises and Design Problems The Static CMOS Inverter An Intuitive Perspective Evaluating the
CHAPTER
1
INTRODUCTION
The evolution of digital circuit design n Compelling issues in digital circuit design n How to measure the quality of a design n Valuable references
1.1 1.2 1.3 1.4 1.5
A Historical Perspective Issues in Digital Integrated
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs)
Borivoje Nikoli
Homework #9
EE 141
Problem #1: Power in CMOS A G1 B C D 50
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
Last modified on November 7, 2002 by Henry Jen and Stanley Wang (henryjen@eecs.berkeley.edu)
Borivoje Nikolic
Homework #9
EECS 141
Problem
second-chapter11-ex.fm Page 1 Friday, October 3, 2003 9:48 PM
1
Chapter 11 Problem Set
Chapter 11 PROBLEMS
1. [E, None, 11.6] For this problem you are given a cell library consisting of full adders and twoinput Boolean logic gates (i.e. AND, OR, I
chapter7-ex.fm Page 1 Wednesday, October 29, 2003 11:52 PM
1
Chapter 7 Problem Set
Chapter 7 PROBLEMS
1. [M, None, 7.4] Figure 1 shows a practical implementation of a pulse register. Clock Clk is ideal with 50% duty cycle.
V DD
Q
X
Q
D Clk d
C
Chapter 12 PROBLEMS
1. [E, SPICE, 12.2.1] Use SPICE to compute the access time of the 512 512 NOR ROM of Example 12.4. Use a simplified model (i.e., do not include all the transistors but model their impact on word and bit lines). Compare the obtain
1
Chapter 4 Problem Set
Chapter 4 Problems
1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock network (between the nodes) is 5 mm long, 3 m wide, and is implemented in polysilicon. At each of the terminal nod
1
Chapter 3 Problem Set
Chapter 3 PROBLEMS
For all problems, use the device parameters provided in Chapter 3 (Tables 3.2 and 3.5) and the inside back book cover, unless otherwise mentioned. Also assume T = 300 K by default. 1. [E,SPICE,3.2.2] a. Co
ECE 474: Digital VLSI Design
Review Homework 1
Due Friday 5:00 PM, February 8th
Problem 1 (10pts): Threshold Drops
Using the switch-model rules presented in class, determine the voltages at Vx, Vy, and
Vz. Assume Ron < RBIG < Roff
VDD
VDD
|VTp|=VTn
VDD>4V