UIT
Digital_System:LAB5
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LAB 5 Adder, Subtractor, Multiplier of two signed numbers in 2scomplement form
M c ch c a Lab 5: Tm hi u phng php thi t k m t s m ch s h c nh l m ch c ng, m ch tr v m ch nhn 2 s c d u d i d ng b -2. ~ Part 1: Thi t k m t m ch c n
H thng s (Digital System): Lab 4
BI THC HNH 4 B m (Counters)
Mc ch bi thc hnh 4: hiu v thit k b m
Phn I
Tm hiu v b m tun t (hay cn gi l b m khng ng b hoc ni tip) s dng T flipflop Tng bc thc hin 1. Thit k 3 b m vi yu cu nh sau: B m th 1: M = 8 (M l h s m h
UIT
Digital_System:LAB3
LAB 3 Latch, Flip-flop, Register
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M c ch c a Lab 3: Hi u ho t ng, thi t k Latch, Flip-flop v Register. ~ Part 1: Thi t k m t m ch i n h t s c n gi n nh sau: T ng b c th c hi n: 1. T o m t project Quartus m i, t tn: user_dir/lab3/l
H tthng s (Diigiittall Systtem): Lab 2 H hng s D g a Sys em Lab 2
S v cch hin th ( Numbers and Displays )
Mc ch lab 2: Thit k mch chuyn t s nh phn sang thp phn v mch cng s BCD
Hng dn cch ng gi v ti s dng 1 mch thit k To 1 file .bdf, v mch cn s dng li trn
UIT
Digital_System:LAB1
LAB 1 Switchs, Lights, Multiplexers
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M c ch c a Lab 1: H c cch k t n i n gi n nh ng ng vo v ng ra c a linh li n n FPGA v thi t k m t s m ch i n n gi n s d ng nh ng linh ki n trn Kit DE2 nh l ng vo v ng ra c a m ch thi t k . Trong
Homework10
1. What is clock skew ? What is jitter ? Give examples to
explain them.
2. What are the application of decoder circuit ?
3. What are differences between EEPROM and flash memory?
4. What is duty cycle ?
5. What is fan-out?
6. What is FIFO?
Homework9
1. Given a SRAM memory chip that is 134,217,728 x 4, answer the
following questions:
a. How many address and data pins does this part have?
b. How many bytes of memory are in this part?
c. Show how to use these chips, and any other logic n
Homework8
1. Design an 8-bit register that has parallel load and has a synchronous
reset (reset=0 resets the register).
2. Draw the logic diagram of a 4 bit register with mode selection inputs
S1 and S0. When S1S0=00, there is to be no change in the
Homework7
(Due November 15, 2010)
1. Draw a timing diagram for the following NOR circuit for an SR
latch with the following input changes. Assume a 2.5 ns delay
for each gate. Comment on why we dont let S=R=1 on a latch.
Show your timing diagram to
Homework6
(Due November 08, 2010)
1.
In the equation below, the function greater_than(x3x2x1x0,z3z2z1z0)
is true, if and only if, the numerical value represented by x3x2x1x0 is
greater than the numerical value represented by z3z2z1z0. Similarly
for
Homework5
1. A majority function is defined as a combinational circuit where
the output is equal to 1 if the input variables have more 1s than
0s. The output is 0 otherwise. Design a 3-input majority function.
2. A combinational circuit is defined b
Homework4
1. Determine the Boolean functions for outputs X and Y as a function
of the four inputs in the following circuit:
2. Obtain the truth table for the circuit shown below. Draw an
equivalent circuit for F with fewer NAND gates.
3. How many tr
Homework3
1. Simplify the following Boolean expressions using only the Boolean
theorems in the notes to a minimum number of literals:
a. ABC + ABC + AB
b. (A + B)(A + B)
c. (A + B + AB)(AB + AC + BC)
d. (A + B)C+AB)BD
2. For the Boolean functions E
Homework2
1. Construct a timing diagram for the circuit shown below, assuming inputs
ABC are all low from time 0 to 10, ABC=LLH from time 10 to 20
(where L denotes low, H denotes high), ABC=LHL from time 20 to 30,
ABC=LHH from time 30 to 40, ABC=HLL
Homework1
1. What is the decimal equivalent of the largest binary integer that can be
obtained with (a) 16 bits and (b) 24 bits?
2. Convert the following binary numbers to decimal: (a) 1010010, (b)
10101010.101, and (c) 10100110.
3. Convert the foll