Lecture 16
Logistics
HW5 out, due next wednesday
Last lecture
Finished combinational logic
Introduction to sequential logic and systems
Today
Memory storage elements
Latches
Flip-flops
Flip flops
Stat
Lecture 15
Logistics
HW4 is due today
HW5 posted today
Exam questions: to me
Class feedback
Last lecture
Adders
Today
More on Adder timing issues (hard!)
M
Add ti i i
(h d!)
Summary of Combinational L
Lecture 14
Logistics
Midterm 1: ave 88, median 89, std 9. good job!
HW4 due on Wednesday
Lab5 is going on this week
Last lecture
Multi-level logic
Timing diagrams
Today
Time/space t d offs: P ll l pre
Lecture 13
Logistics
HW4 up, due on Wednesday
Last lecture
PLDs
Today
Multilevel logic
Timing diagrams
Hazards
CSE370, Lecture 9
13
1
The WHY slide
Multilevel logic
So far we talked about 2 level logi
Lecture 12
Logistics
HW4 will be assigned on Wednesday, due 10/29
Lab4 continuing this week
Midterm1 in class on Wednesday this week
Review session Tomorrow (Tuesday) 6pm in TBD
Lots of office hours:
Lecture 11
Logistics
HW3 due now
Lab4 goes on as normal next week
Tuesday review 6pm(ish) place TBD
Last lecture
"Switching-network" logic blocks
Multiplexers and Demultiplexers
Today
PLDs
PLAs
PALs
R
9/29/2008
Lecture 2: Number Systems
Logistics
Webpage is up! http:/www.cs.washington.edu/370
HW1 is posted on the web in the calender - due 10/1 10:30am
Third TA: Tony Chick [email protected]
E
Lecture 10
Logistics
HW3 due Friday (cover materials up to this lecture)
Lab3 going on this week
g g
Midterm 1: a week from today - material up to this lecture
Last lecture
Dont cares
POS minimization
Lecture 3: Boolean Algebra
Logistics
Class email sign up
Homework 1 due on Wednesday
Lab 1 starts this week: go to your session
Last lecture - Numbers
Binary numbers
Base conversion
Number systems for
Lecture 5
x
The WHY slide
Logistics
s
s
s
x
HW1 due today
HW2 available today, due Wed 1/21
Office Hours this week:
s
Me: Friday 10:00-11:00 CSE 668
TA (Josh): Friday 3:30 CSE 002/3
x
s
s
x
x
Last l
Lecture 4
x
The WHY slide
Logistics
s
s
x Logic Gates and Truth Tables
HW1 due Wednesday at start of class
Office Hours:
s
Me: 12:20-1:00 CSE 668 plus one later this week
TAs: Today at 3:30, tomorro
Combinational Logic Design Process
Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification
D
VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES
Identifier (naming) rules: Can consist of alphabet characters, numbers, and underscore First character must be a letter (alphabet) Last character cannot be an u
SEQUENTIAL LOGIC MODELING EXAMPLE USING 2-PROCESS MODELING STYLE First-In First-Out (FIFO) Control Logic VHDL Modeling Example
A common problem in design is constructing a FIFO from a RAM by designing
INTRODUCTION OF HDLS IN THE DESIGN PROCESS
HDL Hardware Description Language
Two principle HDLs currently used:
VHDL VHSIC Hardware Description Language
VHSIC Very High Speed Integrated Circuit
gate
VHDL ENTITIES, ARCHITECTURES, AND PROCESS
VHDL models consist of two major parts: 1) Entity declaration defines the I/O of the model 2) Architectural body describes the operation of the model Format o
VHDL HIERARCHICAL MODELINNG
To incorporate hierarchy in VHDL we must add component declarations and component instantiations to the model. In addition, we need to declare internal signals to interconn
Test Bench
A test bench is usually a simulation-only model used for design verification of some other
model(s) to be synthesized. A test bench is usually easier to develop than a force file when
verif
FSMs in VHDL Using Enumeration Data Types
Consider a falling edge triggered FSM that performs the following state diagram functionality. We
want to write a VHDL model using enumeration data types.
0X
VHDL CONSTRUCTS Sequential Statements: if-then-else general format: example: if (condition) then if (S = 00) then do stuff Z <= A; elsif (condition) then elsif (S = 11) then do more stuff Z <= B; else
VLSI CAD:
Logic to Layout
Rob A. Rutenbar
University of Illinois
Lecture 4.1
Computational Boolean
Algebra Representations:
Satisfiability (SAT), Part 1
Some Terminology
Satisfiability (called SAT fo
L12: Reconfigurable Logic Architectures
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Frank Honore
Prof. Randy Katz (Unified Microelec
L15: VLSI Integration and Performance
Transformations
Acknowledgement:
Materials in this lecture are courtesy of the following sources and are used with permission.
Curt Schurgers
J. Rabaey, A. Chandr
L16: Power Dissipation in Digital Systems
Problem #1: Power Dissipation/Heat
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium proc
100
286 486
8086 386
10
8085
8080
8008
1 4004
0.1
1971 1974 1978
L10: Analog Building Blocks
(OpAmps, A/D, D/A)
Acknowledgement:
Materials in this lecture are courtesy of the following sources and are used with permission.
Dave Wentzloff
L10: 6.111 Spring 2006
Intr
L14: Final Project Kickoff
L14: 6.111 Spring 2006
Introductory Digital Systems Laboratory
1
Schedule - I
Form project teams this week (nothing to turn in)
Project Abstract (Due April 10th in 38-107 by
L8/9: Arithmetic Structures
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Rex Min
Kevin Atkinson
Prof. Randy Katz (Unified Microelectr
L11: Major/Minor FSMs
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Rex Min
L11: 6.111 Spring 2006
Introductory Digital Systems Labora
L6: FSMs and Synchronization
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Rex Min
J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Int