EECE2323
Digital Logic Design Lab
Prelab 2-1
Partial Arithmetic and Logic Unit (ALU)
Begin by reading Sections 1, 2, and 3 of your lab manual. Then answer the following questions.
1
Design the Partial ALU
Create a Verilog module called eightbit palu which
Homework #1
Question 1 (2 pt.)
Obtain a Boolean function F that outputs the right values for each combination of variables a, b, c, and
d, as given in the following truth table:
a
b
c
d
F
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
0
1
1
0
The Single-Cycle Datapath
Branch
RegWrite
0
1
PC
in out
address
instr
Adder4
out
in
AluOp
write
Instruction
memory
25.21
read_index1
read_data1
20.16
read_index2
0
1
15.11
RegDst
15.0
MemWrite
op1 F
zero
result
AluSrc
read_data2
write_index
0
1
op2 ALU
wr
Unit 6
Support Material
Block Diagrams
Complete datapath
The block diagram below includes the complete datapath and presents the control signals exposed by
each hardware component introduced in the design process. The datapath supports a set of arithmetic
Unit 4
Support Material
Sequential Logic Review
The simplest storage unit
The simplest stable circuit storing one bit can be created with a cycle of NOT gates, where the output
of one gate is connected to the output of the other. When this circuit is swit
EECE2322
Devin Davies
Homework #1
1) Obtain a Boolean function F that outputs the right values for each combination of variables
a) ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
b) ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
2) Which of the following expressions ar
Homework #7
Question 1 (5 pt.)
The following diagram represents the single-cycle datapath studied in class with support for a subset of
the MIPS arithmetic-logic instructions, plus lw, sw, and beq. Control signals appear highlighted in blue.
Branch
RegWri
EECE2323
Digital Logic Design Lab
Prelab 1
Eight Bit Adder
Begin by reading Sections 1 and 2 of your lab manual. Then answer the following questions. Submit
your answers on Blackboard before the deadline.
1. Complete the table below for the expected input
EECE2323
Digital Logic Design Lab
Lab 1
8-bit Adder
1
Objective
In this lab you will create an 8-bit adder with overflow flag using Verilog. This lab is divided into
two parts; in the first part you will design the adder in Verilog and simulate it. In the
EECE2323
Digital Logic Design Lab
Lab 2
Partial Arithmetic and Logic Unit
1
Objective
In this and the next lab you will design a combinatorial circuit known as an Arithmetic and Logic
Unit (ALU) that performs certain calculations on binary inputs.
For thi
Homework #6
For this homework assignment you need to submit the following files on Blackboard:
File q1.s containing the MIPS code for question 1.
File q2.s containing the MIPS code for question 2.
File hw6.pdf containing the rest of your answers.
Questio
Homework #2 Solution
Question 1 (2 pt.)
Write a Verilog module that implements an 8-bit magnitude comparator. The module should combine
two 4-bit magnitude comparators, implemented as a separate module (you can use the code given in
class for these). The
ECE2322 Fall 2012
ECE U322
Digital Logic Design
Sept 17, 2012
Negative Logic and NANDs and NORs
Standard Forms
SOP and POS
Minterms and Maxterms
Lab 1: Hex to 7 segment decoder
Reading: Mano Section 2.5, 2.6, 2.7
Homework 2 due September 20
Quiz 1: Co
ECE 2322 Fall 2012
ECE 2322
Digital Logic Design
Sept. 6, 2012
Lecture 2:
Number Representation
Conversion between different bases
decimal, binary, octal and hex
Unsigned and signed values
Reading: Mano and Ciletti 1.2, 1.3, 1.4, 1.6
We are skippin
ECE2322 Fall 2012
ECE 2232
Digital Logic Design
Sept 12 and 13, 2012
Homework:
HW1 due Thursday, Sept 13
HW2 due Thursday, Sept 20
Topics:
Binary numbers review
Boolean Algebra
Boolean Logic
NOTs, NANDs, and NORs
Reading: Mano Section 2.1 through 2.4
ECE 2322 Fall 2012
ECE 2322
Digital Logic Design
Prof. Miram Leeser
[email protected]
September 5, 2012
Lecture 1:
Organization
Course Policies
Overview
What is Digital Logic ?
Why use Digital Logic ?
lect01.ppt
Two ECE3222 Sections
Monday, Wednesday, Thur
ECE2322 Fall 2012
ECE U322
Digital Logic Design
Sept 19 and 20, 2012
Standard Forms
SOP and POS
Minterms and Maxterms
Minimization: Karnaugh Maps
Reading: Mano Section 2.5, 2.6, 2.7, 3.1, 3.2
Homework 2 due September 20
Homework 3 due September 27
Quiz
EECE2322
ECE U322
Digital Logic Design
Sept 26, 2012
Lecture 10:
Karnaugh Maps
SOP and POS
Dont cares
Reading:
Mano 3.1, 3.2, 3.3, 3.4
Homework 3 due Thursday, Sept 27
lect10.ppt
ECE U322 F12
Midterm in class on Thurs, Oct 4
First Midterm is Thurs
ECE2232
ECE 2322
Digital Logic Design
Oct 1, 2012
Lectures 12:
Multiplexers
Binary Adders
Binary Subtractors
Reading: Mano Section 4.5
Midterm 1 October 4
lect12.ppt
ECE 2322 F12
First Midterm Oct 4 in class
Exam is closed book, closed notes, no el
Unit 5
Support Material
The MARS simulator
From all available MIPS simulation tools, the MARS simulator is a good option for our course. MARS
is an open-source, cross-platform simulator written in Java, available in the following website:
http:/courses.mi