ELEC 5200-001/6200-001 (Fall 2012)
Homework 2 Solution
Assigned 8/27/12, due 9/5/12
Problem 1: Write the MIPS instructions that produce the following binary code. Interpret
the action of each instruction:
(a) 000000 00000 00000 00000 00000 000000
(b) 0000
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test 1, February 10, 2012
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6)
problems. Be sure to revise your answers
ELEC 5200-001/6200-001 (Fall 2012)
Homework 2 Problems
Assigned 8/27/12, due 9/5/12
Problem 1: Write the MIPS instructions that produce the following binary code. Interpret
the action of each instruction:
(a) 000000 00000 00000 00000 00000 000000
(b) 0000
ELEC 5200/ELEC 6200 Computer Architecture and Design
Final Exam, May 4, 2012
Broun 306, 12:00PM2:30PM
Total 25 points
Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to
revise your answers before tur
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test 1, October 6, 2010
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be
sure to revise your answers be
ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2012
Homework 9 Solution
Assigned 4/9/12, due 4/18/12
Problem 1: Run times for three programs are recorded on two processors:
Program
A
B
C
D
Run time (seconds)
Processor X
Processor Y
1
20
20
ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2012
Homework 9 Problems
Assigned 4/9/12, due 4/18/12
Problem 1: Run times for three programs are recorded on two processors:
Program
A
B
C
D
Run time (seconds)
Processor X
Processor Y
1
20
20
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test 1, March 8, 2010
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be
sure to revise your answers befo
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2008 Homework 5 Solution Assigned 3/10/08, due 3/24/08
Problem 1: We can consider a single-cycle datapath as a one-stage pipeline. Suppose it consists of combinational and asynchronous circuit
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test 1, February 10, 2012
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6)
problems. Be sure to revise your answers
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test 2, April 15, 2011
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6)
problems. Be sure to revise your answers bef
ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2012
Homework 8 Solution
Assigned 4/2/12, due 4/9/12
Problem 1:
(a) A one-level SRAM cache has n times shorter cycle time compared to the main
memory. Show that it will provide an average memo
ELEC 5200-001/6200-001 Computer Architecture and Design
Fall 2011
Homework 7 Solution
Assigned 11/9/11, due 11/14/11
Problem 1:
(a) A one-level SRAM cache has n times faster cycle time compared to the main
memory. Show that it will provide an average memo
ELEC 5200-001/6200-001 (Spring 2010)
Homework 2 Solution
Problem 1: How many IAS instructions require memory data access? List those that do not require
memory data access. Not counting pseudoinstructions, list those MIPS instructions that require
memory
Problem 1. What are the five parts of a digital computer?
Answer: Five parts of a computer are datapath, control, memory, input and output.
Problem 2: Define following architectures in one sentence each:
a. Harvard architecture
b. Von Neumann architecture
ELEC 5200-001/6200-001 (Spring 2016)
Homework 1
Peijie Chen
Problem 1: John von Neumann and Alan M. Turing are deemed to have the most
influence on the modern computer architecture. Identify one contribution from each that
you consider most significant. I
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test I, March 5, 2008
Broun 306, 11:00-11:50AM
Total 24 points
Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be
sure to revise your answers bef
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test I, March 5, 2007
Total 24 points
Problem 1:
5 points
Implement a pseudoinstruction to move data from a memory location whose address is in rsrc
register to another memory location whose addre
ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2009
Homework 3 Solution
Assigned 2/9/09, due 2/20/09
Problem 1: For a MIPS computer that has no hardware multiply instruction implemented, write
assembly code to multiply integers a and b, wh
ELEC 5200-001/6200-001 (Fall 2009)
Homework 2 Solution
Problem 1: It is decided to increase the size of the main memory of the IAS computer. The words are
still 40 bits wide and an instruction still has a 20-bit binary representation. What is the
largest
ELEC 5200-001/6200-001 (Fall 2010)
Homework 1 Solution
Assigned 8/30/10, due 9/6/10
Problem 1: Show that for the instruction set of an IAS computer that packs k instructions per word, the
word size is given by:
B = k log2 (N W)
where
N
W
=
=
bits
maximum
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test I, September 19, 2008
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all four (4) problems.
Be sure to revise your answer
Class Test 1, October 16, 2009
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6)
problems. Be sure to revise your answers before turning them in. Please number your
answer shee
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test I, March 6, 2009
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt any four out of the first
five problems. Be sure to revis
ELEC 5200/6200 Spring 2007
Homework # 1 Solution
1). 2-bit full adder:Code:entity twobitadder is
port(
a
: in bit_vector(1 downto 0);
b
: in bit_vector(1 downto 0);
cin : in bit;
s
: out bit_vector(1 downto 0);
cout : out bit
);
end twobitadder;
architect
ELEC 5200-001/6200-001 (Spring 2011)
Homework 1 Solution
Problem 1. What are the five parts of a digital computer?
Answer: Five parts of a computer are datapath, control, memory, input and output.
Problem 2: Define following architectures in one sentence
ELEC 5200/ELEC 6200 Computer Architecture and Design
Class Test 2, April 11, 2012
Broun 306, 11:00-11:50AM
Total 25 points
Instructions: Please read all problems before writing your answers. Attempt all six (6)
problems. Be sure to revise your answers bef
ELEC 5200-001/6200-001 (Spring 2012)
Homework 10 Solution
Assigned 4/18/12, due 4/25/12
Problem 1: The control of a five-cycle multicycle MIPS processor is a finite state
machine with 30 states. The instruction set has 96 instructions and contains a six-b
ELEC 5200-001/6200-001 (Spring 2012)
Homework 6 Solution
Assigned 3/5/12, due 3/19/12
Problem 1: Suppose for a computer, Tm is the time required for reading or writing the
memory, Tf is the time for reading or writing the register file, Ta is the critical
ELEC 5200-001/6200-001 (Spring 2012)
Homework 5 Solution
Assigned 2/24/12, due 3/2/12
Problem 1: Consider two types of MIPS datapaths. The clock rates for single-cycle and
multicycle implementations are 200MHz and 1GHz, respectively. The following
subrout