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School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 Digital Logic Circuits Summer 2012 Final Review Solutions Problem 1: What is the output of the following circuit if the delay of each inverter is 1/6 nanosecond? OUTPUT Answer: The output is inverted every ! nanosecond. The circuit will produce
School: Auburn
Course: Advanced Vlsi Design
ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Tools for Power Analysis http:/www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr13/course.html Murali Dharan January 9, 2013 1 Course Objectives Understand the need for low power in VLSI desig
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Linear Programming A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawa
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770: Advanced VLSI Design Spring 2014 Analog and Radio Frequency (RF) Testing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_S
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Sprin
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Constraint Graph and Retiming Solution Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr
School: Auburn
Course: Special Topics In Electrical Engineering Frequency Synth Ic Dsn
Vector Generation using Spectral Methods Ayoush M Dixit Electrical and Computer Engineering Department Auburn University, Auburn, AL-36849 Email: dixitam@auburn.edu Abstract Two new test generation algorithms for combinational and sequential circuits have
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Introduction to ASIC Design Victor P. Nelson Refer to Michael J. S. Smith Application-Specific Integrated Circuits Application-Specific IC (ASIC) Designed for a specific application Source: N. Weste, CMOS VLSI Design Progress of State of the Art Year 1938
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Automated Synthesis from HDL models Leonardo (Mentor Graphics), Design Compiler (Synopsys) ASIC Design Flow Behavioral Model Synthesis DFT/BIST & ATPG VHDL/Verilog Gate-Level Netlist DRC & LVS Verification Verify Function Full-custom IC Test vectors Stand
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Simulation Testbench Design The Test Bench Concept Project simulations Behavioral/RTL verify functionality 1. Model in VHDL/Verilog Drive with force file or testbench Post-Synthesis 2. Synthesized gate-level VHDL/Verilog netlist Technology-specific V
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Post-Synthesis Simulation VITAL Models, SDF Files, Timing Simulation Post-synthesis simulation Purpose: Synthesis tool generates: Gate-level netlist in VHDL and/or Verilog Standard Delay Format (SDF) file of estimated delays GDK technology directory: Veri
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Design Examples Multiplier (from Smith text, Chapter 10) 4-bit multiplier (hierarchical design) (Smith Chap. 10.2) 1-bit full adder entity Full_Adder is generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X,Y, Cin: in BI
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Multiplier Design (Nelson model) System Example: 8x8 multiplier Multiplicand Multipliplier multiplicand (M) Start Clock controller (C) adder (ADR) Done accumulator (A) Product multiplier (Q) Multiply Algorithm INIT A <- 0 M <-
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Final Exam, December 8, 2011 Broun 113, 4:00-6:30PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them i
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 18, 2013 Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 1, 2013 Total 25 points Problem 1: (3 points) A pipelined MIPS datapath may write a new branch address to the program counter (PC) in the execute cycle in case the branch is taken. This
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Ch 2 Homework 1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 2 Solution Assigned 9/2/11, due 9/12/11 Problem 1: Using the method of positive binary integer multiplication, multiply 4-bit 2s complement integers, 1110 1101, to obtain an 8-bit result. Show the st
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2010) Homework 2 Solution Problem 1: How many IAS instructions require memory data access? List those that do not require memory data access. Not counting pseudoinstructions, list those MIPS instructions that require memory
School: Auburn
Course: Microelectronic Fabrication
Safety Rules and Guidelines Introduction This manual is intended to provide procedure and safety information for all users of the Auburn University Microelectronics Laboratory (AMSTC) facilities. Users are expected to be familiar with the information in t
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 6 DC Measurements II R. M. Nelms revised by John Y. Hung July 6, 2011 Abstract The objectives of this laboratory session are: Review Thevenins and Nortons theorems Measure direct current (dc) electrical quantities such as voltage, current, an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 13 Electrical Measurements in AC Circuits Bei Zhang July 1, 2011 Abstract The objectives of this session are to: Expand usage of the DMM within the National Instruments (NI) ELVIS II+ system, as applied to ac measurements. Teach students how
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 14 Analysis of Variable-frequency Networks Using the NI ELVIS II+ System Bei Zhang July 8, 2011 Abstract The objectives of this session are to: Using NI ELVIS II+ system to investigate networks excited with variable-frequency sinusoidal signal
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 11 MultiSim: AC Analysis Suraj Sindia June 14, 2011 Abstract The objectives of this session are: To learn ac steady state circuit calculations Learn to perform ac analysis using MultiSim circuit simulator Contents 1 Preliminaries: Building an
School: Auburn
Course: Electric Circuit Analysis
Pspice Tutorial Setup *do not forget to include schematics part during set up process. After installation you will have the compenents seen below. Start Pspice Schematics as seen in the picture. Other compenents will start automaticly as they are needed.
School: Auburn
Course: Electric Circuit Analysis
ELEC 2110 Lab 3 Exericse 1: Vo = 150 V Ix = -1.25 A Exercise 2: Vo = 7.693 V P6V = 6*4.615m = 27.69 mW (supplied) 3. Vo as Vin is varied from 50V to 150V: Ix as I1 is varied from -5A to 5A: 4. Vo (voltage across Rb) as a function of resistance, Rb: X-Trac
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 2 Introduction to PSpice: DC Analysis R. M. Nelms revised by John Y. Hung and Suraj Sindia July 22, 2011 Abstract The objectives of this laboratory session are: Become familiar with the basic features and capabilities of the circuit simulation
School: Auburn
Course: Electric Circuit Analysis
Lab 3 Solutions: Exercise 1 (20 points): Vo = 150V Ix = -1.25A Exercise 2 (20 points): Vo = 7.69V Power supplied by 6V source = VI = 6V(4.615mA) = 27.69 mW Exercise 3 (20 points): DC Sweep of Vo: 180V 160V 140V 120V 50V V( Vout ) 60V 70V 80V 90V 100V 110V
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 1 Basic Electrical Measurements R. M. Nelms revision by John Y. Hung June 7, 2011 Abstract The objectives of this laboratory session are: Learn and apply principles of electrical safety Learn to connect basic electrical circuits Learn to use
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 MICROELECTRONIC FABRICATION Fall 2014 Instructor: Mark L. Adams, Ph.D. Contact Information: Office: TBD Phone: TBD Email: mla0019@auburn.edu Lab Instructor: Charles Ellis Office: AERL / F-Lab 0535 Email: elliscd@auburn.edu If you choose to
School: Auburn
Course: Microwave And Rf Engineering
ELEC 5340/6340: RF & Microwave Engineering (TR 8:00-9:15 BRN 239) Fall Semester 2014 Instructor: Stu Wentworth (stuartw@eng.auburn.edu) Office Hours: posted Office: Broun 305 (ph. 844-1878) Primary Text: David M. Pozar, Microwave Engineering, 4th Edition,
School: Auburn
Course: Embedded Computing Systems
ELEC5260/6260 - Embedded Computing Systems Spring Term, 2014 Catalog Data: ELEC 5260/6260. EMBEDDED COMPUTING SYSTEMS (3). Pr. ELEC 2220 or COMP 3350. The design of systems containing embedded computers. Microcontroller technology, assembly language and C
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (Elective for ELEC, ECPE) 2011 Catalog Data: ELEC 5250/6250. COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (3) LEC. 3. Pr., ELEC 2220 or COMP 3350. Computer-automated design of digital logic
School: Auburn
Course: Electrical Engineering Laboratory IV
COURSE SYLLABUS ELEC 3040 ELECTRICAL SYSTEM DESIGN LABORATORY ELEC 3050 EMBEDDED SYSTEM DESIGN LABORATORY FALL SEMESTER, 2011 INSTRUCTORS: Victor P. Nelson, Office: Broun 326, Email: nelsovp@auburn.edu John Y. Hung, Office: Broun 227, Email: hungjoh@aubur
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 - DIGITAL LOGIC CIRCUITS SUMMER SEMESTER - 2011 2011 Catalog Data: ELEC 2200. DIGITAL LOGIC CIRCUITS (3). Prereq. COMP 1200 or COMP 1210. Electronic devices and digital circuits; binary numbers; Boolean algebra and switching functions; gates and
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Ch 2 Homework 1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 2 Solution Assigned 9/2/11, due 9/12/11 Problem 1: Using the method of positive binary integer multiplication, multiply 4-bit 2s complement integers, 1110 1101, to obtain an 8-bit result. Show the st
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Final Exam, December 8, 2011 Broun 113, 4:00-6:30PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them i
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2010) Homework 2 Solution Problem 1: How many IAS instructions require memory data access? List those that do not require memory data access. Not counting pseudoinstructions, list those MIPS instructions that require memory
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 18, 2013 Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Problem 2: For two variables a and b of a Boolean algebra, use the axioms to
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 1, 2013 Total 25 points Problem 1: (3 points) A pipelined MIPS datapath may write a new branch address to the program counter (PC) in the execute cycle in case the branch is taken. This
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 6 Solution Assigned 10/17/11, due 10/24/10 Problem 1: A house alarm system is designed to sense several conditions represented by binary (0,1) Boolean variables, A, F, M, and W, defined as: A F M W =
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Answer: The minimized function, as shown on the following K
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Problems Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270-001/6270-001 Low-Power Design of Electronic Circuits Homework 2 Solution Problem 1: A 32 bit bus operates at 1.0V and 2GHz clock rate. Each bit wire, driven by a CMOS buffer, has a total capacitance of 2pF. Each wire has a toggling probability o
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Problem 2: Sketch a two-level AND-OR gate-level circuit for
School: Auburn
1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server: ftp.ns.warea
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Answer: Postulate 6 requires that every element must have a unique complement
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Solution Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 Digital Logic Circuits Summer 2012 Final Review Solutions Problem 1: What is the output of the following circuit if the delay of each inverter is 1/6 nanosecond? OUTPUT Answer: The output is inverted every ! nanosecond. The circuit will produce
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Class Test II, October 12, 2011 Broun 113, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: Advanced Vlsi Design
ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Tools for Power Analysis http:/www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr13/course.html Murali Dharan January 9, 2013 1 Course Objectives Understand the need for low power in VLSI desig
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Linear Programming A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawa
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770: Advanced VLSI Design Spring 2014 Analog and Radio Frequency (RF) Testing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_S
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Sprin
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Constraint Graph and Retiming Solution Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Timing Verification and Optimization Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr1
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Retiming Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Spring 2014, Fe
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Verification Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Spring 2014
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Timing Simulation and STA Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.ht
School: Auburn
Course: Advanced Vlsi Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2014 Datapath and Control (Chapter 4) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http:/www.eng.auburn.
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Introduction Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 2014, Jan 13 ELE
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770-001, Spring 2014 Homework # 4 Solution Assigned: Friday, April 4, 2014 Due: Friday, April 11, 2014 Problem 1: A Bluetooth transmitter amplifier operates over a frequency band 2.4 2.5GHz. It is specified to have a minimum gain of 22dB and a gain
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770-001, Spring 2014 Homework # 3 Solution Assigned: Monday, March 17, 2014 Due: Monday, March 24, 2014 Problem 1: A ripple carry adder is made of full adder cells each having 1 unit of combinational delay. To convert a four-bit ripple carry adder i
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770-001 Advanced VLSI Design Spring 2014 Homework 2 Assigned 2/19/14, due 3/3/14 Problem 1: Design two 16-bit combinational multiplier circuits, one for area optimization and the other for delay optimization. Create a miter circuit to apply the simu
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Introduction to ASIC Design Victor P. Nelson Refer to Michael J. S. Smith Application-Specific Integrated Circuits Application-Specific IC (ASIC) Designed for a specific application Source: N. Weste, CMOS VLSI Design Progress of State of the Art Year 1938
School: Auburn
Course: VLSI Testing
SOC Testing Adit D. Singh Electrical & Computer Engineering Auburn University adsingh@eng.auburn.edu l 1 05/18/01 V4.3 SOC Testing This two-day short course provides a strong basic understanding of the systematic methods employed for developing testing pr
School: Auburn
Course: VLSI Testing
Test Compression BIST has not been widely adopted because it requires significant circuit modification for Test point insertion to improve coverage X-state elimination for deterministic response compression Test Compression methods attempt to achieve a ke
School: Auburn
Course: VLSI Testing
Design for Testability Theory and Practice Professors Adit Singh & Vishwani Agrawal Electrical & Computer Engineering Bangalore, July 27-30, 1 Auburn University 05/18/01 V4.3 Design for Testability Theory and Practice Presenters: Adit D. Singh is James B.
School: Auburn
Course: VLSI Testing
BIST Built-In Self-Test Copyright 2001, Agrawal & Test: Lecture 25 VLSI Bushnell 1 BIST Process Test controller Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if ver
School: Auburn
Course: Embedded Computing Systems
Embedded Computing Platforms Chapter 4 (Sections 4.1-4.4) 1 Platform components CPUs. Interconnect buses. Memory. Input/output devices. Implementations: System-on-Chip (SoC) vs. Multi-Chip 2 Microcontroller vs. microprocessor Commercial off-the-shelf (COT
School: Auburn
Course: Embedded Computing Systems
Formal System Design Process with UML Use a formal process & tools to facilitate and automate design steps: Requirements Specification System architecture Coding/chip design Testing Text: Chapter 1.3,1.4 Object-Oriented Design Describe system/design as i
School: Auburn
Course: Embedded Computing Systems
Example: Model Train Controller Purposes of example: Follow a design through several levels of abstraction. Gain experience with UML. Model train setup rcvr motor power supply console header address command ECC Requirements Console can control 8 trains o
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #8 Solutions
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Automated Synthesis from HDL models Leonardo (Mentor Graphics), Design Compiler (Synopsys) ASIC Design Flow Behavioral Model Synthesis DFT/BIST & ATPG VHDL/Verilog Gate-Level Netlist DRC & LVS Verification Verify Function Full-custom IC Test vectors Stand
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Simulation Testbench Design The Test Bench Concept Project simulations Behavioral/RTL verify functionality 1. Model in VHDL/Verilog Drive with force file or testbench Post-Synthesis 2. Synthesized gate-level VHDL/Verilog netlist Technology-specific V
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Post-Synthesis Simulation VITAL Models, SDF Files, Timing Simulation Post-synthesis simulation Purpose: Synthesis tool generates: Gate-level netlist in VHDL and/or Verilog Standard Delay Format (SDF) file of estimated delays GDK technology directory: Veri
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Design Examples Multiplier (from Smith text, Chapter 10) 4-bit multiplier (hierarchical design) (Smith Chap. 10.2) 1-bit full adder entity Full_Adder is generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X,Y, Cin: in BI
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Multiplier Design (Nelson model) System Example: 8x8 multiplier Multiplicand Multipliplier multiplicand (M) Start Clock controller (C) adder (ADR) Done accumulator (A) Product multiplier (Q) Multiply Algorithm INIT A <- 0 M <-
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Simulation Using Mentor Graphics Modelsim SE ASIC Design Flow Behavioral Model Verify Function VHDL/Verilog Synthesis DFT/BIST & ATPG Gate-Level Netlist Full-custom IC Test vectors Standard Cell IC & FPGA/CPLD DRC & LVS Verification Verify Function T
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 Digital Logic Circuits Summer 2012 Final Review Solutions Problem 1: What is the output of the following circuit if the delay of each inverter is 1/6 nanosecond? OUTPUT Answer: The output is inverted every ! nanosecond. The circuit will produce
School: Auburn
Course: Advanced Vlsi Design
ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Tools for Power Analysis http:/www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr13/course.html Murali Dharan January 9, 2013 1 Course Objectives Understand the need for low power in VLSI desig
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Linear Programming A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawa
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770: Advanced VLSI Design Spring 2014 Analog and Radio Frequency (RF) Testing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_S
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Sprin
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Constraint Graph and Retiming Solution Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Timing Verification and Optimization Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr1
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Retiming Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Spring 2014, Fe
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Verification Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Spring 2014
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Timing Simulation and STA Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.ht
School: Auburn
Course: Advanced Vlsi Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2014 Datapath and Control (Chapter 4) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http:/www.eng.auburn.
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Introduction Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 2014, Jan 13 ELE
School: Auburn
Course: VLSI Testing
SOC Testing Adit D. Singh Electrical & Computer Engineering Auburn University adsingh@eng.auburn.edu l 1 05/18/01 V4.3 SOC Testing This two-day short course provides a strong basic understanding of the systematic methods employed for developing testing pr
School: Auburn
Course: VLSI Testing
Design for Testability Theory and Practice Professors Adit Singh & Vishwani Agrawal Electrical & Computer Engineering Bangalore, July 27-30, 1 Auburn University 05/18/01 V4.3 Design for Testability Theory and Practice Presenters: Adit D. Singh is James B.
School: Auburn
Course: VLSI Testing
BIST Built-In Self-Test Copyright 2001, Agrawal & Test: Lecture 25 VLSI Bushnell 1 BIST Process Test controller Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if ver
School: Auburn
Course: Embedded Computing Systems
Embedded Computing Platforms Chapter 4 (Sections 4.1-4.4) 1 Platform components CPUs. Interconnect buses. Memory. Input/output devices. Implementations: System-on-Chip (SoC) vs. Multi-Chip 2 Microcontroller vs. microprocessor Commercial off-the-shelf (COT
School: Auburn
Course: Embedded Computing Systems
Formal System Design Process with UML Use a formal process & tools to facilitate and automate design steps: Requirements Specification System architecture Coding/chip design Testing Text: Chapter 1.3,1.4 Object-Oriented Design Describe system/design as i
School: Auburn
Course: Embedded Computing Systems
Example: Model Train Controller Purposes of example: Follow a design through several levels of abstraction. Gain experience with UML. Model train setup rcvr motor power supply console header address command ECC Requirements Console can control 8 trains o
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 27: Review for MidTerm Exam 2 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline HW Solutions and Lecture Notes Posted to Canvas Mid Term Exam 2 Study Guide (also on Canvas) Useful
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 14: Review for MidTerm Exam 1 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline 2 HW Solutions and Lecture Notes Posted to BlackBoard Mid Term Exam 1 Study Guide (also on BlackBoar
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Course Information Notice: This outline may be revised at any time during the term Course Objective: This course is designed to develop an understanding of the fundamentals of integrated circuit (i.e., microelectronic) processing technology
School: Auburn
Name (4 points): A Solution ELEC-3500 Spring 2012 Exam #2 This is a closed book exam, but one 8.5 11-inch sheet of notes and a calculator may be used. Absolutely no wireless services (including cell phones) may be used during the exam. The four problems a
School: Auburn
School: Auburn
Course: Digital Signal Processing
R. Review Materials Contents R1 Mathematical Formulas and Identities R1.1 Finite and Innite Sums of Numbers1 . . . . . R1.2 Power Series . . . . . . . . . . . . . . . . . . . R1.3 Factorial . . . . . . . . . . . . . . . . . . . . . R1.4 Permutations and C
School: Auburn
Course: Analog Electronics
3700 Exam Review II Topics to be covered: NonidealOperationalAmplifiers SmallSignalModelingandLinearAmplification SingleTransistorsAmplifiers Midterm II on 3/30 (Friday). Midterm II covers chap 3, 4, 5. You may bring two sheets of papers (4 pages double s
School: Auburn
Course: Analog Electronics
BJT Small-Signal Model 3700 Exam Review I Topics to be covered: Cbc Introduction and Review for Microelectronic Devices Ideal Operational Amplifiers depend on bias You may want to summarize your review on a couple of sheets (double sided is OK). Bring a c
School: Auburn
School: Auburn
Course: Special Topics In Electrical Engineering Frequency Synth Ic Dsn
Vector Generation using Spectral Methods Ayoush M Dixit Electrical and Computer Engineering Department Auburn University, Auburn, AL-36849 Email: dixitam@auburn.edu Abstract Two new test generation algorithms for combinational and sequential circuits have
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Introduction to ASIC Design Victor P. Nelson Refer to Michael J. S. Smith Application-Specific Integrated Circuits Application-Specific IC (ASIC) Designed for a specific application Source: N. Weste, CMOS VLSI Design Progress of State of the Art Year 1938
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Automated Synthesis from HDL models Leonardo (Mentor Graphics), Design Compiler (Synopsys) ASIC Design Flow Behavioral Model Synthesis DFT/BIST & ATPG VHDL/Verilog Gate-Level Netlist DRC & LVS Verification Verify Function Full-custom IC Test vectors Stand
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Simulation Testbench Design The Test Bench Concept Project simulations Behavioral/RTL verify functionality 1. Model in VHDL/Verilog Drive with force file or testbench Post-Synthesis 2. Synthesized gate-level VHDL/Verilog netlist Technology-specific V
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Post-Synthesis Simulation VITAL Models, SDF Files, Timing Simulation Post-synthesis simulation Purpose: Synthesis tool generates: Gate-level netlist in VHDL and/or Verilog Standard Delay Format (SDF) file of estimated delays GDK technology directory: Veri
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Design Examples Multiplier (from Smith text, Chapter 10) 4-bit multiplier (hierarchical design) (Smith Chap. 10.2) 1-bit full adder entity Full_Adder is generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X,Y, Cin: in BI
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Multiplier Design (Nelson model) System Example: 8x8 multiplier Multiplicand Multipliplier multiplicand (M) Start Clock controller (C) adder (ADR) Done accumulator (A) Product multiplier (Q) Multiply Algorithm INIT A <- 0 M <-
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Simulation Using Mentor Graphics Modelsim SE ASIC Design Flow Behavioral Model Verify Function VHDL/Verilog Synthesis DFT/BIST & ATPG Gate-Level Netlist Full-custom IC Test vectors Standard Cell IC & FPGA/CPLD DRC & LVS Verification Verify Function T
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Sequential Logic Circuits VHDL Process Construct [label:] process (sensitivity list) declarations begin sequential statements end process; Process statements are executed in sequence Process statements are executed once at star
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Finite State Machines and Controllers Modeling Finite State Machines (Synchronous Sequential Circuits) FSM design & synthesis process: 1. 2. 3. 4. 5. 6. Design state diagram (behavior) Derive state table Reduce state table Choo
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Arithmetic Functions and IEEE Numeric_std package Smith ASIC text sections: 12.6.5, 12.6.9, 12.6.10 Synthesizing arithmetic circuits (12.6.5, 12.6.9, 12.6.10) Synthesis tool recognizes overloaded operators and generates corresponding circuits: +, -,
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Built-In Self Test Smith Text: Chapter 14.7 Mentor Graphics: LBISTArchitect Process Guide Top-down test design flow Source: FlexTest Manual Built-In Self-Test (BIST) Structured-test techniques for logic circuits to improve access to internal signals from
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Design for Test Scan Test Smith Text: Chapter 14.6 Mentor Graphics Documents: Scan and ATPG Process Guide DFTAdvisor Reference Manual Tessent Common Resources Manual for ATPG Products Top-down test design flow Source: Scan and APTG Process Guide Sequentia
School: Auburn
Course: Computer Aided Design Of Digital Circuits
VHDL Modeling for Synthesis Combinational Logic Circuits VHDL synthesis references LeonardoSpectrum HDL Synthesis Manual Access from Leonardo Help menu or mgcdocs _bk_leospec.pdf Smith Text: Chapter 12 VHDL and Verilog synthesis examples Synopsys Design C
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Modeling & Simulating ASIC Designs with VHDL Reference: Smith text: Chapters 10 & 12 Hardware Description Languages VHDL = VHSIC Hardware Description Language (VHSIC = Very High Speed Integrated Circuits) Developed by DOD from 1983 based on ADA IEEE Stand
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Boundary Scan Smith Text: Chapter 14.2 Top-down test design flow BSDArchitect Source: FlexTest Manual Boundary-Scan Test JTAG (Joint Test Action Group) test standard became IEEE Standard 1149.1 Test Port and Boundary-Scan Architecture Allows boards to b
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Faults, Testing & Test Generation Smith Text: Chapter 14.1,14.3, 14.4 Mentor Graphics/Tessent: Scan and ATPG Process Guide ATPG and Failure Diagnosis Tools Reference Manual (access via mgcdocs) ASIC Design Flow Behavioral Model Verify Function VHDL/Verilo
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250_6250 Project 9 Due: 9 am, Thursday, November 13, 2014 Part 1. (Both ELEC 5250 and 6260 Students.) Create SPICE models of a 3-input NOR gate and an inverter, and simulate the operation of a circuit in ADiT, with the NOR gate output driving the in
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI Design Physical design process overview CMOS transistor structure and fabrication steps Standard cell layouts Creation, verification & characterization of a standard-cell bas
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250_6250 Project 7 Due: Tuesday, October 28, 2014 For this assignment, a project report is to be submitted electronically as a Word or PDF document. We will be using the 2008 icflow design tools and ASIC Design Kit (ADK) for the remaining projects.
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250_6250 Project 8 Due: Thursday, November 6, 2014 ELEC 5250 Students: Do this assignment with the modulo-6 counter circuit (resubmit the first 4 steps from the previous assignment). ELEC 6250 Students: First practice with the modulo-6 counter (do n
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 Project 10 Due: Friday, Nov. 21, 2014 You are to design a test to get as close as possible to 100% fault coverage for the following circuit. 1. Considering all stuck-at faults in this circuit, collapse the fault set by finding equivalent an
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Introduction to ASIC Design Victor P. Nelson Refer to Michael J. S. Smith Application-Specific Integrated Circuits Application-Specific IC (ASIC) Designed for a specific application Source: N. Weste, CMOS VLSI Design Progress of State of the Art Year 1938
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 Project #5 Synthesis Due Friday, October 3, 2014 (3:00 pm) A. BOTH ELEC 5250 and 6250: For the Modulo-5 counter designed previously: 1. Use LeonardoSpectrum to synthesize a gate-level netlist of GDK standard cells, producing both VHDL and V
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 VHDL Project #4 First draft Due Thursday, September 18 (for instructor feedback only no grade) Final version, including test bench and simulation Due Thursday, September 25 Design a hierarchical VHDL register-transfer-level (RTL) model of a
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ASIC Computer-Aided Design Flow ELEC 5250/6250 Lecture 3 Nvidia Tegra 2 SoC Tablet Applications: Asus Eee Pad Motorola Xoom Samsung Galaxy Acer Iconia Tab VLSI D&T Seminar - Victor P. Nelson 2/29/2012 ASIC Design Flow Behavioral Model Verify Function
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 Homework Project 3 VHDL Simulations Part 1 Due Tuesday, September 9 in class Part 2 Due Friday, September 12 at 11am You are to perform four simulations of the modulo-5 counter designed previously. Your tests should be designed to fully ver
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 Homework Project 2 Now that you have designed a gate-level structural model of a modulo-5 counter by hand, we want to (1) verify its correctness through simulation, (2) develop a behavioral model of the counter, which is where we would norm
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 Homework Project 1 Due: Tuesday, 9/2/2014 Design a digital modulo-5 counter with the following characteristics: Three output bits: Q2,Q1,Q0 Synchronous count count up on the rising edge of a clock (CLK) Synchronous load load an external
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ASIC Physical Design Top-Level Chip Layout ELEC 5250/6250 Floorplanning (Text chap. 15, 16) Floorplanning: arrange major blocks prior to detailed layout to minimize chip area input is a netlist of circuit blocks (hierarchical) after system partitioning
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ASIC Physical Design Post-Layout Verification Course Web Page Reference: Designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools ASIC Physical Design (Standard Cell) (can also do full custom layout) Component-Level Netlist
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ASIC Project Cost Smith Text Chapter 1 VLSI Implementations Custom Standard cell Gate array FPGA Density Highest Medium Low Lowest Performance Highest Medium Low Lowest Design time Long Medium Short Shortest Chip Dev cost High Medium Low Lowest Testabilit
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ASIC Physical Design Standard-Cell Design Flow Course Web Page Reference: Designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools ASIC Physical Design (Standard Cell) (can also do full custom layout) Component-Level Netlist
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 6250 Final Project/Exam Fall Semester 2014 Due Tuesday, December 9, by 9:00 a.m. Since this project serves as the final exam, any form of collaboration with others in the class is prohibited. This is to be an individual effort to demonstrate your kno
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250 Final Exam/Project Fall Semester 2014 Due Tuesday, December 9, by 9:00 a.m. Since this project serves as the final exam, any form of collaboration with others in the class is prohibited. This is to be an individual effort to demonstrate your kno
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Post-Layout Simulation Analog and Digital Turbo Simulator (ADiT) Analog &Digital Turbo Simulator (ADiT) Extracted from schematic: design.lvs.netlist Extracted from layout: design.pex.netlist design.pex.netlist.design.pxi Analog &Digital Turbo Simulator (A
School: Auburn
Course: Computer Aided Design Of Digital Circuits
Overlapping vias. Fix by deleting one via and moving one of the metal 2 wires horizontally until the top and bottom parts line up. (Only one via needed to connect metal2 to metal 3.) Metal2 spacing violation between wire and via. Fix by adding a metal2 sh
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 22: Packaging Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Packaging Yield 2 Finished Silicon Wafer 150-mm wafer that has finished the fabrication process Mounted on scree
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 25: MOS Integration Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Outline MOS Integration 2 MOSFET I-V Transfer (ID-VGS) VGS (V) 3 Output (ID-VDS) VDS (V) MOSFET Threshold Voltage Threshold
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 28: MidTerm 2 Examples Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline A few examples relevant to Mid Term 2 Note that this review is not necessarily allinclusivetopics that co
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 20: Back-End Technology 1 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Back-End Technology 1: Interconnects and Contacts 2 Interconnections and Contacts MOS Logic Circuit
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 24 MOS Intro Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Outline Intro to MOS 2 MOS Cap MOSFET Were looking for a voltage controlled switchi.e., a voltage applied to a gate can control th
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 26: M-S and pn Junctions Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Discussion of M-S junctions Discussion of pn junctions A lot of this comes from: http:/ecee.colorado.
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 23: Solid-State Concepts Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Outline Review of Solid-State concepts 2 Why Solid-State? From the electrical engineering perspective, we want to be a
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 18: Etching Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Outline Etching Concepts 2 Etching 3 Etching Oxide Etching Profiles (a) Isotropic etching - wet chemistry - mask undercutting (b) A
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 21: Back-End Technology 2 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Back-End Technology 2: Low R Low k => Low C 2 Interconnections and Contacts MOS Logic Circuit 3 Bas
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 16: Film Deposition 1 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Comments on Mid Term Exam 1 Film Deposition 1 2 Mid Term Exam 1 Comments from you: 3 Mid Term Exam 1 Que
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 19: Mid Term 1 Solutions Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 1) (a) (7pts) What does ITRS stand for (in the context of this class)? International Technology Roadmap for Semiconduc
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 15: Ion Implantation 2 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Ion Implantation 2 Examples Non-idealities 2 Ion Implantation Modeling Mathematical Model (Simple Gaussi
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 11: Diffusion 3 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Diffusion Part 3: 2 Note on erfc plot Diffused Resistors Irwins Curves Resistivity / Dopant Profiling erfc Plot
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 8: Microscopy and Inspection Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Opening comments Please put some care into homework solution preparation Including stapling or otherwise attaching
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 10: Diffusion 2 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Oxidation Examples Diffusion Part 2 2 Oxidation Examples Previous Example: A <100> silicon wafer has 2000 oxid
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 13: Ion Implantation 1 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Join IEEE Ion Implantation 2 Basic concepts Simple model Masking Junction Depths More complex model Ion I
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 9: Diffusion 1 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Diffusion 2 Channel and Parasitic Resistance VG Silicide VS Rcontact Sidewall Spacers Rpoly VD xW Rsource Rext Rch
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 12: Diffusion 4 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Diffusion Part 4: Comment on Example 4.3 Diffusion Example (problem) Diffusion Example (simulation) 2 Diffusio
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 5: Photolithography 3 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Lithography Challenges Advanced Photolithography Techniques: 2 Double Patterning EUV EBL FIB DPN NIL Litho
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 7: Oxidation 2 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline 2 Comment on Si consumption Return to Deal-Grove Model of Oxidation Example Higher order effects Thermal Oxidation
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Introduction and Course Overview Background and Motivation Solid-State Physics and Materials 2 Introduction and Overview See syllabus
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 3: Photolithography Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Photolithography Concepts Photolithographic Process Steps 2 Photolithography Photolithography is the set of
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 6: Oxidation 1 (Kinetics) Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline General Properties of SiO2 Deal-Grove Model of Oxidation 2 General SiO2 Properties ~ Exclusive to Si
School: Auburn
Course: Microelectronic Fabrication
Microelectronics Fabrication ELEC 5730/6730 Lecture 4: Photolithography 2 Fall 2014 Dr. Mark L. Adams ECE Dept. Auburn University 1 Todays Outline Photolithographic Process Steps 2 Photolithography Process 3 Cleaning and preparation of wafer surface Spin
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Final Exam, December 8, 2011 Broun 113, 4:00-6:30PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them i
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 18, 2013 Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 1, 2013 Total 25 points Problem 1: (3 points) A pipelined MIPS datapath may write a new branch address to the program counter (PC) in the execute cycle in case the branch is taken. This
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Class Test II, October 12, 2011 Broun 113, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: VLSI Testing
Test Compression BIST has not been widely adopted because it requires significant circuit modification for Test point insertion to improve coverage X-state elimination for deterministic response compression Test Compression methods attempt to achieve a ke
School: Auburn
Course: Microwave And Rf Engineering
ELEC 5340/6340 Exam #2 11/11/10 Part 1: This portion of the test is pencil only. Name:_ 1. What do we mean when we say a transistor is unilateral? 2. At a particular bias and frequency, a transistors output stability circle (L chart) is shown where the fi
School: Auburn
Course: Microwave And Rf Engineering
ELEC 5340/6340 Exam #2 11/9/04 Name:_ Part 1: This portion of the test is pencil only. 1. What do we mean when we say a transistor is unilateral? 2. The scattering matrix is given for two transistors. Below each one, discuss whatever you can pertaining to
School: Auburn
Course: Microwave And Rf Engineering
ELEC 5340/6340 Final Exam Part I: closed notes, closed book, closed calculator. Name:_ 1. (2 pts each) Define the following in terms of the two port network S-parameters: (a) reciprocal network (b) lossless network (c) insertion loss (d) return loss 2. Tr
School: Auburn
Course: DIGITAL LOGIC CIRCUITS
ELEC 2200-002 Digital Logic Circuits Class Test II, October 22, 2014 Broun 238, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: DIGITAL LOGIC CIRCUITS
ELEC 2200-002 Digital Logic Circuits Class Test I, September 12, 2014 Broun 238, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Final Exam, May 2, 2012 Broun 113, 4:00PM6:30PM Total 35 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before turning them in. Thank you
School: Auburn
Course: Advanced Vlsi Design
Name _ ELEC 7770 Advanced VLSI Design Final Exam, May 4, 2007 Broun 235, 5:00PM-7:30PM Total 35 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before turning them in. T
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 2, April 11, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 28, 2011 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 8, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers befo
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 6, 2009 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt any four out of the first five problems. Be sure to revis
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 28, 2011 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 8, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers befo
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 6, 2009 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt any four out of the first five problems. Be sure to revis
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 5, 2008 Broun 306, 11:00-11:50AM Total 24 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 5, 2007 Total 24 points Problem 1: 5 points Implement a pseudoinstruction to move data from a memory location whose address is in rsrc register to another memory location whose addre
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 19, 2008 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all four (4) problems. Be sure to revise your answer
School: Auburn
Course: Computer Architecture And Design
Class Test 1, October 16, 2009 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your answer shee
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 21, 2007 Total 24 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in.
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 24, 2004 Total 24 points Problem 1: 3 points a. Draw a block diagram of the hardware of a computer identifying each block. b. How do the blocks communicate with each other? c. Wh
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, October 5, 2005 (rescheduled October 7, 2005) Total 24 points Problem 1: 6 points a. Assume that a CPU can perform a multiplication in 12ns, an addition in 1ns and a subtraction in 1.5ns.
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 11, 2006 Total 24 points Problem 1: 8 points a. Assume that a CPU can perform a multiplication in 10ns, an addition in 1ns and a subtraction in 1.5ns. Given that values of a and
School: Auburn
Course: Communication Systems
This image cannot currently be displayed. Example 3.1: Single-tone AM Design factor: modulation factor Mao & Li @ AU 14 This image cannot currently be displayed. Example 3.1 (contd.) Mao & Li @ AU 15 This image cannot currently be displayed. Example 3.1
School: Auburn
Course: Communication Systems
Quantization Noise: Example A full-load sinusoidal m(t) of amplitude Am, average 2 power is: PS Am / 2 Full-load Am=mmax 2 2 Average signal power is: PS Am / 2 mmax / 2 The quantizers output signal-to-noise ratio is: Average signal power (SNR ) O Average
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 (2 pts) Name:_ Test #3: 4/13/11 Part I (25 points): Only a simple instrument of writing is allowed. 1. (5 points) Fill in the following table: Parameter Units Name Time average power density vector P(r, , ) P s m2 Directivity 2. (3 points) How i
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Final Exam Fall 2009 (1 pt) Name:_ Indicate your program: (EE, WIRE, Other): _ (40 pts) Part 1: Simple writing instrument only! 1. (8 pts) Fill in the following grand Maxwells Equation table. Differential form Gausss Law Integral form Gausss Law
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Name:_ Test #3: 11/4/09 Part I (25 points): Only a simple instrument of writing is allowed. 1. (5 points) Fill in the following table: Parameter Units W/m2 P(r, , ) Name Time average power density vector P Dmax Rrad - 2. (2 points) What is the d
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Name:_ Test #2 3/9/11 Part I: Only a simple instrument of writing is allowed. 1. (2 pts)(choose the correct answer) In air-filled rectangular waveguide, the cutoff frequency for the TE10 mode is primarily determined by: (a) the long dimension a
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Final Exam Spring 2011 (1 pt) Name:_ (35 pts) Part 1: Pencil only! 1. (1 pts each) FillinthefollowinggrandMaxwellsEquationtable. Differential form GausssLaw Integral form GausssLaw for Mag. Fields FaradaysLaw AmperesCircuit Law 2. (1 pt each) Fi
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Sample Test #1 Summer 2009 Name:_ Part I: Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. Fill in the following table. Symbol Name (what the symbol represents in Stan
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 (1 pt) Name:_ Test #2 10/5/09 Part I: Only a simple instrument of writing is allowed. 1. (2 pts)(choose the correct answer) In air-filled rectangular waveguide, the cutoff frequency for the TE01 mode is primarily determined by: (a) the metal con
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Test #1 Fall 2009 (1 pt) Name:_ Part I: Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (8 pts) The electric field of a propagating wave is given by: E = 2.5e-0.020y
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Test #1 Name:_ Spring 2011 Part I: Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (5 pts)A material has constitutive properties . At an angular frequency : (a) give
School: Auburn
Course: Electrical
ELEC 3310 Test #3 Name:_ Spring 09, 4/10/09 Part I (4 points each): Closed notes/closed calculator/pencil only 1. Give the formula for the Law of Biot-Savart. Identify the units for each component. 2. Give the formulaforAmperesCircuitLaw.Identifytheunitsf
School: Auburn
Course: Electrical
ELEC 3310 Final Exam Spring 2009 Name:_ Part I (40 points): Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (5points) Fill in the following table. Symbol Name (what the symbol
School: Auburn
Course: Electrical
ELEC 3310 Test #3 (1 point) Name:_ Fall 10, 11/11/10 Part I (4 points each): Closed notes/closed calculator/pencil only 1. What is the formula for the Lorentz force equation? What are the standard units associated with eac h term in this equation? 2.Givet
School: Auburn
Course: Electrical
ELEC 3310 Final Exam Fall 2010 (1 pt) Name:_ Part I (45 points): Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (8 points) Fill in the following table. Symbol Name (what the s
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Class Test, April 6, 2009 Total 25 points Broun 125, 3:00-3:50PM Problem 1 (6 points): In a CMOS cell library, every two-input combinational gate (inverting, noninverting or exclusive-OR type) co
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Ch 2 Homework 1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 2 Solution Assigned 9/2/11, due 9/12/11 Problem 1: Using the method of positive binary integer multiplication, multiply 4-bit 2s complement integers, 1110 1101, to obtain an 8-bit result. Show the st
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2010) Homework 2 Solution Problem 1: How many IAS instructions require memory data access? List those that do not require memory data access. Not counting pseudoinstructions, list those MIPS instructions that require memory
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Problem 2: For two variables a and b of a Boolean algebra, use the axioms to
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 6 Solution Assigned 10/17/11, due 10/24/10 Problem 1: A house alarm system is designed to sense several conditions represented by binary (0,1) Boolean variables, A, F, M, and W, defined as: A F M W =
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Answer: The minimized function, as shown on the following K
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Problems Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270-001/6270-001 Low-Power Design of Electronic Circuits Homework 2 Solution Problem 1: A 32 bit bus operates at 1.0V and 2GHz clock rate. Each bit wire, driven by a CMOS buffer, has a total capacitance of 2pF. Each wire has a toggling probability o
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Problem 2: Sketch a two-level AND-OR gate-level circuit for
School: Auburn
1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server: ftp.ns.warea
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Answer: Postulate 6 requires that every element must have a unique complement
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Solution Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770-001, Spring 2014 Homework # 4 Solution Assigned: Friday, April 4, 2014 Due: Friday, April 11, 2014 Problem 1: A Bluetooth transmitter amplifier operates over a frequency band 2.4 2.5GHz. It is specified to have a minimum gain of 22dB and a gain
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770-001, Spring 2014 Homework # 3 Solution Assigned: Monday, March 17, 2014 Due: Monday, March 24, 2014 Problem 1: A ripple carry adder is made of full adder cells each having 1 unit of combinational delay. To convert a four-bit ripple carry adder i
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770-001 Advanced VLSI Design Spring 2014 Homework 2 Assigned 2/19/14, due 3/3/14 Problem 1: Design two 16-bit combinational multiplier circuits, one for area optimization and the other for delay optimization. Create a miter circuit to apply the simu
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #8 Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Chapter 4 Homework Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #9a Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #7 Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #6 Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #1 Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #5b Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #5a Solutions
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Homework #2 Solutions 3.1 Using Fig. 3.6 with 100 nm = 0.1 m: (a) Wet O2 yields 0.15 hours or approximately 9 minutes. (b) Dry O2 yields 2.3 hours. Nine minutes is too short for good control, so the dry oxidation cycle would be preferred. 3
School: Auburn
Course: Microwave And Rf Engineering
ELEC 5340/6340 MWO Amplifier Design Project Design amplifier for maximum gain at 2.4 GHz using open-ended shunt stub microstrip matching networks. System impedance is 50 . Use Mitsubishi FET: MGF1601b o Path in Elements palette: Libraries AWR Web Site Par
School: Auburn
ELEC 5120/6120 Homework Solution 5 With error detection, all odd number of errors can be detected. So after parity check, the remaining (undetected errors) are even-number errors, i.e., 2-, 4-bit errors either in the first byte or in the second byte. P1 =
School: Auburn
Homework5 NingkaiTang Prob. 6.2: A data source produces 7-bit IRA characters. Derive an expression of the maximum effective data rate (rate of IRA data bits) over an x-bps line for the following: (a) Asynchronous transmission, with a 1.5unit stop element
School: Auburn
ELEC 5120/6120 Homework Assignment 5 Problems 6.2, 6.10, 6.13, 6.14(b)(c), and 6.17 in Chapter 6. Prob. 6.2: A data source produces 7-bit IRA characters. Derive an expression of the maximum effective data rate (rate of IRA data bits) over an x-bps line fo
School: Auburn
Homework4 NingkaiTang Prob. 4.3: Given a 100 W power source, what is the maximum allowed length for the following transmission media if a signal of 1 W is to be received? (a) 24-gauge (0.5 mm) twisted pair operating at 300 kHz. (b) 24gauge (0.5 mm) twiste
School: Auburn
ELEC 5120/6120 Homework 4 Homework assignment 4: Problems 4.3, 4.14, 4.15, 5.6, 5.9 and 5.10 in the textbook. The problems are: Prob. 4.3: Given a 100 W power source, what is the maximum allowed length for the following transmission media if a signal of 1
School: Auburn
ELEC 5120/6120 Homework Solution 3 3.21 C = B log2(1 + SNR) 20 106 = 3 106 log2(1 + SNR) log2(1 + SNR) = 6.67 1 + SNR = 102 SNR = 101 3.23 (Eb/N0) = 151 dBW 10 log 2400 10 log 1500 + 228.6 dBW = 12 dBW Source: [FREE98] 4.1 Elapsed time = (5000 km)/(1000 k
School: Auburn
ELEC 5120/6120 Homework 2 Homework assignment 2: Problems 3.13, 3.14, 3.15, 3.16, and 3.19 in the textbook. The problems are: Prob. 3.13 (a) Suppose that a digitized TV picture is to be transmitted from a source that uses a matrix of 480*500 picture elem
School: Auburn
ELEC 5120/6120 Homework 3 Homework assignment 3: Problems 3.21, 3.23, 4.1, 4.2, and 4.17 in the textbook. The problems are: Prob. 3.21: Given a channel with an intended capacity of 20 Mbps, the bandwidth of the channel is 3 MHz. Assuming white thermal noi
School: Auburn
ELEC 5120/6120 Homework Solution 2 3.13 a. (30 pictures/s) (480 500 pixels/picture) = 7.2 106 pixels/s Each pixel can take on one of 32 values and can therefore be represented by 5 bits: R = 7.2 106 pixels/s 5 bits/pixel = 36 Mbps b. We use the formula: C
School: Auburn
Homework3 NingkaiTang Prob. 3.21: Given a channel with an intended capacity of 20 Mbps, the bandwidth of the channel is 3 MHz. Assuming white thermal noise, what signal-to-noise ratio is required to achieve this capacity? Answer:C= 20*1000000=3*1000000* S
School: Auburn
Homework11 NingkaiTang Question 13.1: When a node experiences saturation with respect to incoming packets, what general strategy may be used? Answer:Wehave3generalstrategies. 1. Congestioncontrol:Whichwillallowstreamratetuningduringtransmissionto ensureco
School: Auburn
Homework2 NingkaiTang Prob. 3.13 (a) Suppose that a digitized TV picture is to be transmitted from a source that uses a matrix of480*500 picture elements (pixels), where each pixel can take on one of 32 intensive values. Assume that 30 pictures are sent p
School: Auburn
ELEC 5120/6120 Homework 1 Homeworkassignment1:Problems2.3,2.5,2.6,2.8,and10.4inthetextbook(8thedition). Theproblemsare: Prob.2.3:Listthemajordisadvantageswiththelayeredapproachtoprotocols. Prob.2.6:InFigure2.2,exactlyoneprotocoldataunit(PDU)inlayerNise
School: Auburn
ELEC 5120/6120 Homework Solution 1 2.3 Perhaps the major disadvantage is the processing and data overhead. There is processing overhead because as many as seven modules (OSI model) are invoked to move data from the application through the communications s
School: Auburn
ELEC 5120/6120 Homework Assignment 9 Question 10.6: What is the significance of packet size in a packet-switching network? Problem 10.2: (a) If a crossbar matrix has n input lines and m output lines, how many crosspoints are required. (b) How many crosspo
School: Auburn
Homework1 NingkaiTang Prob. 2.3: List the major disadvantages with the layered approach to protocols. Answer:1.Protocolstandardsmaybemuchmorecomplexwithmorelayers.Wehaveto makeeveryprotocolsatisfythefunctionofeachlayerandpreciselyservetheupperlayer. So,wh
School: Auburn
ELEC 5120/6120 Homework Assignment 11 Question 13.1: When a node experiences saturation with respect to incoming packets, what general strategy may be used? Question 13.3: Give a brief explanation of each of the congestion control techniques illustrated i
School: Auburn
Homework9 NingkaiTang Question 10.6: What is the significance of packet size in a packet-switching network? Answer: Packetsizemayaffecttheefficiencyofnetwork.Whenseparatepacketinto smallerpiecescanexploitpipelinetechnologybetterforwecantransmitmorepackets
School: Auburn
ELEC 5120/6120 Homework Solution 11 Q13.1 Two general strategies can be adopted. The first such strategy is to discard any incoming packet for which there is no available buffer space. The alternative is for the node that is experiencing these problems to
School: Auburn
ELEC 5120/6120 Homework Assignment 10 Question 12.4: What are the advantages and disadvantages of adaptive routing? Prob. 12.1: Consider a packet switching network of N nodes, connected by the following topologies: (i) Star: once central node with no atta
School: Auburn
Homework10 NingkaiTang Question 12.4: What are the advantages and disadvantages of adaptive routing? Answer:Advantages: 1. Canrecoverfromnodefailure; 2. Candealwithcongestion; 3. Betterperformancebasedonthe2pointsabove. Disadvantages: 1. Additionalworkonc
School: Auburn
ELEC 5120/6120 Homework Solution 10 12.4 Advantages: (1) An adaptive routing strategy can improve performance, as seen by the network user. (2) An adaptive routing strategy can aid in congestion control. Because an adaptive routing strategy tends to balan
School: Auburn
ELEC 5120/6120 Homework Solution 8 Problem 1: Problem 2: Problem 3: Problem 4:
School: Auburn
Homework8 NingkaiTang Problem 1: We have a pure ALOHA network with 100 stations. If Tfr=1 us, what is the number of frames/s each station can send to achieve the maximum efficiency Answer:Aswewanttoachievethemaximumefficiency *Numberofframes/s*Numberofsta
School: Auburn
ELEC 5120/6120 Homework Assignment 8 Problem 1: We have a pure ALOHA network with 100 stations. If Tfr=1 us, what is the number of frames/s each station can send to achieve the maximum efficiency? Problem 2: Repeat Additional Prob. 1 for slotted ALOHA. Pr
School: Auburn
Homework7 NingkaiTang Question 8.6: Why is a statistical time division multiplexer more efficient than a synchronous time division multiplexer? Answer:StatisticalTDMisastateorientedmethod.ItisdifferentfromTDMforitwill allocateresourcedependingontheirusage
School: Auburn
Homework6 NingkaiTang Prob. 7.3: A channel has a data rate of 4 kbps and a propagation delay of 20 ms. For what range of frame sizes does stop-and-wait give an efficiency of at least 50%? Answer:Toreach50%,wehavetheequation: Transmissiontime/(Propagationt
School: Auburn
ELEC 5120/6120 Homework Assignment 7 Question 8.6, Problems 8,1, 8.2, 8.7, and 8.8 in Chapter 8 of the textbook. Question 8.6: Why is a statistical time division multiplexer more efficient than a synchronous time division multiplexer? Prob. 8.1: The infor
School: Auburn
ELEC 5120/6120 Homework Assignment 6 Problems 7.3, 7.4, 7.5, 7.7, and 7.10 in Chapter 7 of the textbook. Prob. 7.3: A channel has a data rate of 4 kbps and a propagation delay of 20 ms. For what range of frame sizes does stop-and-wait give an efficiency o
School: Auburn
Course: Microelectronic Fabrication
Safety Rules and Guidelines Introduction This manual is intended to provide procedure and safety information for all users of the Auburn University Microelectronics Laboratory (AMSTC) facilities. Users are expected to be familiar with the information in t
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 6 DC Measurements II R. M. Nelms revised by John Y. Hung July 6, 2011 Abstract The objectives of this laboratory session are: Review Thevenins and Nortons theorems Measure direct current (dc) electrical quantities such as voltage, current, an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 13 Electrical Measurements in AC Circuits Bei Zhang July 1, 2011 Abstract The objectives of this session are to: Expand usage of the DMM within the National Instruments (NI) ELVIS II+ system, as applied to ac measurements. Teach students how
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 14 Analysis of Variable-frequency Networks Using the NI ELVIS II+ System Bei Zhang July 8, 2011 Abstract The objectives of this session are to: Using NI ELVIS II+ system to investigate networks excited with variable-frequency sinusoidal signal
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 11 MultiSim: AC Analysis Suraj Sindia June 14, 2011 Abstract The objectives of this session are: To learn ac steady state circuit calculations Learn to perform ac analysis using MultiSim circuit simulator Contents 1 Preliminaries: Building an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 12 Problem Solving: Analysis of AC Circuits R. M. Nelms revised by Suraj Sindia July 7, 2011 Abstract The objectives of this session are: Practice solving ac circuits. Learn how to perform complex number calculations in MATLAB. Contents 1 Sol
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 10 PSpice: AC Analysis R. M. Nelms revised by Bei Zhang July 9, 2011 Abstract The objectives of this session are to: Perform ac steady-state circuit calculations Learn PSpice ac analysis Contents 1 Performing an AC Analysis using PSpice 1.1 D
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 9 Problem Solving: First-order Transient Circuits R. M. Nelms revised by Suraj Sindia July 6, 2011 Abstract The objectives of this session are: Learn to solve transient circuits analytically. Learn to plot analytical expressions in MATLAB. L
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 8 Electrical Measurements: First-order Transient Circuits R. M. Nelms revised by John Y. Hung July 18, 2011 Abstract The objectives of this laboratory session are: Learn how to make measurements using an oscilloscope. Learn how to experimenta
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 7 Problem Solving Using Thevenins & Nortons Theorems R. M. Nelms revised by Suraj Sindia July 6, 2011 Abstract The objectives of this session are: Learn how to determine the Thevenin and Norton equivalent circuits for a given circuit. Learn t
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 5 Problem Solving: Mesh & Nodal Analysis R. M. Nelms revised by Suraj Sindia July 6, 2011 Abstract The objectives of this session are: Learn to solve for current through and voltage across any element in a circuit. Learn to use Kirchos voltag
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 4 Introduction to Virtual Instruments: DC Measurements I Suraj Sindia June 30, 2011 Abstract The objectives of this session are: Learn to use virtual instruments to apply stimulus to electric circuits and capture their response. Learn to use
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 3 Introduction to MultiSim: DC Analysis Bei Zhang and Suraj Sindia July 1, 2011 Abstract The objectives of this session are to: Help students become familiar with the basic features of MultiSim, a circuit simulation software tool Provide an i
School: Auburn
Course: Electrical Engineering
t: CLkris Trueblood 'Prroon:. Mo.44ket.4 Ca.);ro Deck ; Awn. t, 22, Loos ?rot oeb, je StA. h -c4 s kkaira., au . eiu Sclii tnt c exmci ?Toro, 5-3E9 t s I fri4roamc-Kor el to-4- e.0 11 / lean, 4. t; Id enet01 '4.SQ fl4Qtpan i 44 Anwlec Lear" "-La
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 10 PRELAB Your Name Pages of 6 54\ Prelab Questions (10 points) Answer these questions before coming to lab and turn them in when you arrive. You may do your work on separate paper (for example you might want t
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 9 Prelab Page 6 of 6 Prelab Questions (10 points) Answer these questions before coming to lab and turn them in when you arrive. You may do your work on separate paper (for example you might want to do your work o
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 7 PRELAB I Page 4 of 4 Your Name (V) ICA C,WirOS Prelab Questions (10 points) Answer these questions before coming to lab and turn them in when you arrive. You may do your work on separate paper (for example
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 1 - Prelab Page 8 of 8 /L9 Your Name c.ittitc 0S Prelab Questions and Quiz (20 points) (Answer these questions in lab and turn them into your instructor before beginning the in-lab procedure. For subsequent weeks,
School: Auburn
School: Auburn
Jordan Ward ELEC 3030 RF Systems Lab Audio Amplifier Pre-Lab September 15, 2011 2. PQ = _ 4. PQ = _ 6. PQ = _ 8. PQ = _ 1. 3. 4. 5. 7. 8.
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040/3050 Lab 5 Matrix Keypad Interface Using Parallel I/O Goals of this lab exercise Control a peripheral device with the MC9S12C32 microcontroller Use parallel I/O ports to control and access a device Implement program-controlled and/or interrup
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC3040/ 3050 Lab Manual Lab 5 Revised 2/09/11 LAB 5: MATRIX KEYPAD INTERFACE USING PARALLEL I/O THE VELLEMAN 16-KEY MATRIX KEYPAD The purpose of this lab is to use the MC9S12C32 (HCS12) microcontroller to control a peripheral device, interfaced through
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC3040/ 3050 Lab Manual Lab 4 Revised 9/7/2011 LAB 4: INTERRUPT PROCESSING IN C INTRODUCTION The previous labs worked with simple input/output (I/O) devices using programcontrolled I/O; the programs continuously monitored each device to determine when t
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040/3050 Lab Manual Lab 3 Revised 9/9/11 LAB 3: SYSTEM ANALYSIS & DEBUGGING WITH OSCILLOSCOPE AND LOGIC ANALYZER INTRODUCTION The purpose of this lab is to continue to gain experience with designing and testing microcontroller-based systems, and to
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040/3050 Lab Manual Lab 2 Revised 8/19/11 LAB 2: Developing and Debugging C Programs in CodeWarrior for the HCS12 Microcontroller The objective of this laboratory session is to become more familiar with the process for creating, executing and debugg
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040 Electrical System Design Lab ELEC 3050 Embedded System Design Lab Lab Session 1 Project Creation and Debugging The objective of this laboratory session is to become familiar with the process for creating, executing and debugging application prog
School: Auburn
Course: Electric Circuit Analysis
Pspice Tutorial Setup *do not forget to include schematics part during set up process. After installation you will have the compenents seen below. Start Pspice Schematics as seen in the picture. Other compenents will start automaticly as they are needed.
School: Auburn
Course: Electric Circuit Analysis
ELEC 2110 Lab 3 Exericse 1: Vo = 150 V Ix = -1.25 A Exercise 2: Vo = 7.693 V P6V = 6*4.615m = 27.69 mW (supplied) 3. Vo as Vin is varied from 50V to 150V: Ix as I1 is varied from -5A to 5A: 4. Vo (voltage across Rb) as a function of resistance, Rb: X-Trac
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 2 Introduction to PSpice: DC Analysis R. M. Nelms revised by John Y. Hung and Suraj Sindia July 22, 2011 Abstract The objectives of this laboratory session are: Become familiar with the basic features and capabilities of the circuit simulation
School: Auburn
Course: Electric Circuit Analysis
Lab 3 Solutions: Exercise 1 (20 points): Vo = 150V Ix = -1.25A Exercise 2 (20 points): Vo = 7.69V Power supplied by 6V source = VI = 6V(4.615mA) = 27.69 mW Exercise 3 (20 points): DC Sweep of Vo: 180V 160V 140V 120V 50V V( Vout ) 60V 70V 80V 90V 100V 110V
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 1 Basic Electrical Measurements R. M. Nelms revision by John Y. Hung June 7, 2011 Abstract The objectives of this laboratory session are: Learn and apply principles of electrical safety Learn to connect basic electrical circuits Learn to use
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 MICROELECTRONIC FABRICATION Fall 2014 Instructor: Mark L. Adams, Ph.D. Contact Information: Office: TBD Phone: TBD Email: mla0019@auburn.edu Lab Instructor: Charles Ellis Office: AERL / F-Lab 0535 Email: elliscd@auburn.edu If you choose to
School: Auburn
Course: Microwave And Rf Engineering
ELEC 5340/6340: RF & Microwave Engineering (TR 8:00-9:15 BRN 239) Fall Semester 2014 Instructor: Stu Wentworth (stuartw@eng.auburn.edu) Office Hours: posted Office: Broun 305 (ph. 844-1878) Primary Text: David M. Pozar, Microwave Engineering, 4th Edition,
School: Auburn
Course: Embedded Computing Systems
ELEC5260/6260 - Embedded Computing Systems Spring Term, 2014 Catalog Data: ELEC 5260/6260. EMBEDDED COMPUTING SYSTEMS (3). Pr. ELEC 2220 or COMP 3350. The design of systems containing embedded computers. Microcontroller technology, assembly language and C
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (Elective for ELEC, ECPE) 2011 Catalog Data: ELEC 5250/6250. COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (3) LEC. 3. Pr., ELEC 2220 or COMP 3350. Computer-automated design of digital logic
School: Auburn
Course: Electrical Engineering Laboratory IV
COURSE SYLLABUS ELEC 3040 ELECTRICAL SYSTEM DESIGN LABORATORY ELEC 3050 EMBEDDED SYSTEM DESIGN LABORATORY FALL SEMESTER, 2011 INSTRUCTORS: Victor P. Nelson, Office: Broun 326, Email: nelsovp@auburn.edu John Y. Hung, Office: Broun 227, Email: hungjoh@aubur
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 - DIGITAL LOGIC CIRCUITS SUMMER SEMESTER - 2011 2011 Catalog Data: ELEC 2200. DIGITAL LOGIC CIRCUITS (3). Prereq. COMP 1200 or COMP 1210. Electronic devices and digital circuits; binary numbers; Boolean algebra and switching functions; gates and
School: Auburn
Course: Computer Systems
ELEC 2220 - COMPUTER SYSTEMS Summer 2010 2010 Catalog Data: ELEC 2220. COMPUTER SYSTEMS (3) LEC, 3. Pr., ELEC 2210 or ELEC 2200. Computer hardware and software organization, processor programming models, data representation, assembly language programming,