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School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 Digital Logic Circuits Summer 2012 Final Review Solutions Problem 1: What is the output of the following circuit if the delay of each inverter is 1/6 nanosecond? OUTPUT Answer: The output is inverted every ! nanosecond. The circuit will produce
School: Auburn
Course: Special Topics In Electrical Engineering Frequency Synth Ic Dsn
Vector Generation using Spectral Methods Ayoush M Dixit Electrical and Computer Engineering Department Auburn University, Auburn, AL-36849 Email: dixitam@auburn.edu Abstract Two new test generation algorithms for combinational and sequential circuits have
School: Auburn
ELEC 5120/6120: Telecommunication Networks Introduction Mao, Auburn University Communication Networks Problem How to provide connection to a given set of devices that want to exchange information Device: telephone, computer, terminals, etc. Simple Soluti
School: Auburn
Telecommunication Networks Circuit Switching and Packet Switching Mao, Auburn University Switched Network Mao, Auburn University 2 Nodes A collection of nodes and connections is a communications network Nodes may connect to other nodes only, or to stati
School: Auburn
Telecommunication Networks Protocol Architecture, TCP/IP, and Internet-Based Applications Mao, Auburn University Protocol Architecture, TCP/IP, and Internet-Based Applications To destroy communication completely, there must be no rules in common between
School: Auburn
Telecommunication Networks Congestion in Data Networks Mao, Auburn University What Is Congestion? Congestion occurs when the no of packets being transmitted through the network approaches the packet handling capacity of the network Congestion control aim
School: Auburn
Telecommunication Networks Routing in Switched Networks Mao, Auburn University Traditional Circuit Switching Mao, Auburn University 2 Space Division Switch 0 1 A crosspoint Mao, Auburn University 3 Switched Network Mao, Auburn University 4 Routing in
School: Auburn
Telecommunication Networks Data Transmission (a) Mao, Auburn University Data Transmission Mao, Auburn University 2 Transmission Terminology Data transmission occurs between a transmitter & receiver via some medium Guided medium e.g., twisted pair, coaxi
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Final Exam, December 8, 2011 Broun 113, 4:00-6:30PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them i
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 18, 2013 Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 1, 2013 Total 25 points Problem 1: (3 points) A pipelined MIPS datapath may write a new branch address to the program counter (PC) in the execute cycle in case the branch is taken. This
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Ch 2 Homework 1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 2 Solution Assigned 9/2/11, due 9/12/11 Problem 1: Using the method of positive binary integer multiplication, multiply 4-bit 2s complement integers, 1110 1101, to obtain an 8-bit result. Show the st
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2010) Homework 2 Solution Problem 1: How many IAS instructions require memory data access? List those that do not require memory data access. Not counting pseudoinstructions, list those MIPS instructions that require memory
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 6 DC Measurements II R. M. Nelms revised by John Y. Hung July 6, 2011 Abstract The objectives of this laboratory session are: Review Thevenins and Nortons theorems Measure direct current (dc) electrical quantities such as voltage, current, an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 13 Electrical Measurements in AC Circuits Bei Zhang July 1, 2011 Abstract The objectives of this session are to: Expand usage of the DMM within the National Instruments (NI) ELVIS II+ system, as applied to ac measurements. Teach students how
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 14 Analysis of Variable-frequency Networks Using the NI ELVIS II+ System Bei Zhang July 8, 2011 Abstract The objectives of this session are to: Using NI ELVIS II+ system to investigate networks excited with variable-frequency sinusoidal signal
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 11 MultiSim: AC Analysis Suraj Sindia June 14, 2011 Abstract The objectives of this session are: To learn ac steady state circuit calculations Learn to perform ac analysis using MultiSim circuit simulator Contents 1 Preliminaries: Building an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 12 Problem Solving: Analysis of AC Circuits R. M. Nelms revised by Suraj Sindia July 7, 2011 Abstract The objectives of this session are: Practice solving ac circuits. Learn how to perform complex number calculations in MATLAB. Contents 1 Sol
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 10 PSpice: AC Analysis R. M. Nelms revised by Bei Zhang July 9, 2011 Abstract The objectives of this session are to: Perform ac steady-state circuit calculations Learn PSpice ac analysis Contents 1 Performing an AC Analysis using PSpice 1.1 D
School: Auburn
Course: Electric Circuit Analysis
Pspice Tutorial Setup *do not forget to include schematics part during set up process. After installation you will have the compenents seen below. Start Pspice Schematics as seen in the picture. Other compenents will start automaticly as they are needed.
School: Auburn
Course: Electric Circuit Analysis
ELEC 2110 Lab 3 Exericse 1: Vo = 150 V Ix = -1.25 A Exercise 2: Vo = 7.693 V P6V = 6*4.615m = 27.69 mW (supplied) 3. Vo as Vin is varied from 50V to 150V: Ix as I1 is varied from -5A to 5A: 4. Vo (voltage across Rb) as a function of resistance, Rb: X-Trac
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 2 Introduction to PSpice: DC Analysis R. M. Nelms revised by John Y. Hung and Suraj Sindia July 22, 2011 Abstract The objectives of this laboratory session are: Become familiar with the basic features and capabilities of the circuit simulation
School: Auburn
Course: Electric Circuit Analysis
Lab 3 Solutions: Exercise 1 (20 points): Vo = 150V Ix = -1.25A Exercise 2 (20 points): Vo = 7.69V Power supplied by 6V source = VI = 6V(4.615mA) = 27.69 mW Exercise 3 (20 points): DC Sweep of Vo: 180V 160V 140V 120V 50V V( Vout ) 60V 70V 80V 90V 100V 110V
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 1 Basic Electrical Measurements R. M. Nelms revision by John Y. Hung June 7, 2011 Abstract The objectives of this laboratory session are: Learn and apply principles of electrical safety Learn to connect basic electrical circuits Learn to use
School: Auburn
Course: Embedded Computing Systems
ELEC5260/6260 - Embedded Computing Systems Spring Term, 2014 Catalog Data: ELEC 5260/6260. EMBEDDED COMPUTING SYSTEMS (3). Pr. ELEC 2220 or COMP 3350. The design of systems containing embedded computers. Microcontroller technology, assembly language and C
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (Elective for ELEC, ECPE) 2011 Catalog Data: ELEC 5250/6250. COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (3) LEC. 3. Pr., ELEC 2220 or COMP 3350. Computer-automated design of digital logic
School: Auburn
Course: Electrical Engineering Laboratory IV
COURSE SYLLABUS ELEC 3040 ELECTRICAL SYSTEM DESIGN LABORATORY ELEC 3050 EMBEDDED SYSTEM DESIGN LABORATORY FALL SEMESTER, 2011 INSTRUCTORS: Victor P. Nelson, Office: Broun 326, Email: nelsovp@auburn.edu John Y. Hung, Office: Broun 227, Email: hungjoh@aubur
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 - DIGITAL LOGIC CIRCUITS SUMMER SEMESTER - 2011 2011 Catalog Data: ELEC 2200. DIGITAL LOGIC CIRCUITS (3). Prereq. COMP 1200 or COMP 1210. Electronic devices and digital circuits; binary numbers; Boolean algebra and switching functions; gates and
School: Auburn
Course: Computer Systems
ELEC 2220 - COMPUTER SYSTEMS Summer 2010 2010 Catalog Data: ELEC 2220. COMPUTER SYSTEMS (3) LEC, 3. Pr., ELEC 2210 or ELEC 2200. Computer hardware and software organization, processor programming models, data representation, assembly language programming,
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Ch 2 Homework 1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 2 Solution Assigned 9/2/11, due 9/12/11 Problem 1: Using the method of positive binary integer multiplication, multiply 4-bit 2s complement integers, 1110 1101, to obtain an 8-bit result. Show the st
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Final Exam, December 8, 2011 Broun 113, 4:00-6:30PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them i
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2010) Homework 2 Solution Problem 1: How many IAS instructions require memory data access? List those that do not require memory data access. Not counting pseudoinstructions, list those MIPS instructions that require memory
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 18, 2013 Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Problem 2: For two variables a and b of a Boolean algebra, use the axioms to
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 1, 2013 Total 25 points Problem 1: (3 points) A pipelined MIPS datapath may write a new branch address to the program counter (PC) in the execute cycle in case the branch is taken. This
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 6 Solution Assigned 10/17/11, due 10/24/10 Problem 1: A house alarm system is designed to sense several conditions represented by binary (0,1) Boolean variables, A, F, M, and W, defined as: A F M W =
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Answer: The minimized function, as shown on the following K
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Problems Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270-001/6270-001 Low-Power Design of Electronic Circuits Homework 2 Solution Problem 1: A 32 bit bus operates at 1.0V and 2GHz clock rate. Each bit wire, driven by a CMOS buffer, has a total capacitance of 2pF. Each wire has a toggling probability o
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Problem 2: Sketch a two-level AND-OR gate-level circuit for
School: Auburn
1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server: ftp.ns.warea
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Answer: Postulate 6 requires that every element must have a unique complement
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Solution Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 Digital Logic Circuits Summer 2012 Final Review Solutions Problem 1: What is the output of the following circuit if the delay of each inverter is 1/6 nanosecond? OUTPUT Answer: The output is inverted every ! nanosecond. The circuit will produce
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Class Test II, October 12, 2011 Broun 113, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
ELEC 5120/6120: Telecommunication Networks Introduction Mao, Auburn University Communication Networks Problem How to provide connection to a given set of devices that want to exchange information Device: telephone, computer, terminals, etc. Simple Soluti
School: Auburn
Telecommunication Networks Circuit Switching and Packet Switching Mao, Auburn University Switched Network Mao, Auburn University 2 Nodes A collection of nodes and connections is a communications network Nodes may connect to other nodes only, or to stati
School: Auburn
Telecommunication Networks Protocol Architecture, TCP/IP, and Internet-Based Applications Mao, Auburn University Protocol Architecture, TCP/IP, and Internet-Based Applications To destroy communication completely, there must be no rules in common between
School: Auburn
Telecommunication Networks Congestion in Data Networks Mao, Auburn University What Is Congestion? Congestion occurs when the no of packets being transmitted through the network approaches the packet handling capacity of the network Congestion control aim
School: Auburn
Telecommunication Networks Routing in Switched Networks Mao, Auburn University Traditional Circuit Switching Mao, Auburn University 2 Space Division Switch 0 1 A crosspoint Mao, Auburn University 3 Switched Network Mao, Auburn University 4 Routing in
School: Auburn
Telecommunication Networks Data Transmission (a) Mao, Auburn University Data Transmission Mao, Auburn University 2 Transmission Terminology Data transmission occurs between a transmitter & receiver via some medium Guided medium e.g., twisted pair, coaxi
School: Auburn
Telecommunication Networks Multiplexing Mao, Auburn University How to Share a Link Multiplexing Frequency division multiplexing (FDM) Time division multiplexing (TDM) Wavelength division multiplexing (WDM) Code division multiple access (CDMA) Interleave
School: Auburn
Telecommunication Networks Signal Encoding Techniques Mao, Auburn University Signal Encoding Techniques Mao, Auburn University 2 Digital Data, Digital Signal Line coding Digital signal discrete, discontinuous voltage pulses each pulse is a signal elemen
School: Auburn
Telecommunication Networks Random Access From Data Communications and Networking, Behrouz A. Forouzan Mao, Auburn University Multiple Access Mao, Auburn University 2 Random Access ALOHA Carrier Sense Multiple Access Carrier Sense Multiple Access with Co
School: Auburn
Telecommunication Networks Data Transmission (b) Mao, Auburn University Data and Signals Data: analog or digital Signal: analog or digital Represent analog data by Analog signals Digital signals Represent digital data by Digital signals Analog signals M
School: Auburn
Telecommunication Networks Transmission Media Mao, Auburn University Overview Transmission medium and physical layer From Data Communications and Networking, Behrouz A. Forouzan Mao, Auburn University 2 Classes of Transmission Media Characteristics and
School: Auburn
Telecommunication Networks Digital Data Communications Techniques Mao, Auburn University Asynchronous and Synchronous Transmission Timing problems require a mechanism to synchronize the transmitter and receiver receiver samples stream at bit intervals if
School: Auburn
Telecommunication Networks Data Link Control Protocols Mao, Auburn University Data Link Control Protocols The logic layer above the physical layer Requirements and objectives for effective data communication framing and frame synchronization flow control
School: Auburn
ELEC 5120/6120 Homework Solution 5 With error detection, all odd number of errors can be detected. So after parity check, the remaining (undetected errors) are even-number errors, i.e., 2-, 4-bit errors either in the first byte or in the second byte. P1 =
School: Auburn
Homework5 NingkaiTang Prob. 6.2: A data source produces 7-bit IRA characters. Derive an expression of the maximum effective data rate (rate of IRA data bits) over an x-bps line for the following: (a) Asynchronous transmission, with a 1.5unit stop element
School: Auburn
ELEC 5120/6120 Homework Assignment 5 Problems 6.2, 6.10, 6.13, 6.14(b)(c), and 6.17 in Chapter 6. Prob. 6.2: A data source produces 7-bit IRA characters. Derive an expression of the maximum effective data rate (rate of IRA data bits) over an x-bps line fo
School: Auburn
Homework4 NingkaiTang Prob. 4.3: Given a 100 W power source, what is the maximum allowed length for the following transmission media if a signal of 1 W is to be received? (a) 24-gauge (0.5 mm) twisted pair operating at 300 kHz. (b) 24gauge (0.5 mm) twiste
School: Auburn
ELEC 5120/6120 Homework 4 Homework assignment 4: Problems 4.3, 4.14, 4.15, 5.6, 5.9 and 5.10 in the textbook. The problems are: Prob. 4.3: Given a 100 W power source, what is the maximum allowed length for the following transmission media if a signal of 1
School: Auburn
ELEC 5120/6120 Homework Solution 3 3.21 C = B log2(1 + SNR) 20 106 = 3 106 log2(1 + SNR) log2(1 + SNR) = 6.67 1 + SNR = 102 SNR = 101 3.23 (Eb/N0) = 151 dBW 10 log 2400 10 log 1500 + 228.6 dBW = 12 dBW Source: [FREE98] 4.1 Elapsed time = (5000 km)/(1000 k
School: Auburn
ELEC 5120/6120 Homework 2 Homework assignment 2: Problems 3.13, 3.14, 3.15, 3.16, and 3.19 in the textbook. The problems are: Prob. 3.13 (a) Suppose that a digitized TV picture is to be transmitted from a source that uses a matrix of 480*500 picture elem
School: Auburn
ELEC 5120/6120 Homework 3 Homework assignment 3: Problems 3.21, 3.23, 4.1, 4.2, and 4.17 in the textbook. The problems are: Prob. 3.21: Given a channel with an intended capacity of 20 Mbps, the bandwidth of the channel is 3 MHz. Assuming white thermal noi
School: Auburn
ELEC 5120/6120 Homework Solution 2 3.13 a. (30 pictures/s) (480 500 pixels/picture) = 7.2 106 pixels/s Each pixel can take on one of 32 values and can therefore be represented by 5 bits: R = 7.2 106 pixels/s 5 bits/pixel = 36 Mbps b. We use the formula: C
School: Auburn
Homework3 NingkaiTang Prob. 3.21: Given a channel with an intended capacity of 20 Mbps, the bandwidth of the channel is 3 MHz. Assuming white thermal noise, what signal-to-noise ratio is required to achieve this capacity? Answer:C= 20*1000000=3*1000000* S
School: Auburn
Homework11 NingkaiTang Question 13.1: When a node experiences saturation with respect to incoming packets, what general strategy may be used? Answer:Wehave3generalstrategies. 1. Congestioncontrol:Whichwillallowstreamratetuningduringtransmissionto ensureco
School: Auburn
Homework2 NingkaiTang Prob. 3.13 (a) Suppose that a digitized TV picture is to be transmitted from a source that uses a matrix of480*500 picture elements (pixels), where each pixel can take on one of 32 intensive values. Assume that 30 pictures are sent p
School: Auburn
ELEC 5120/6120 Homework 1 Homeworkassignment1:Problems2.3,2.5,2.6,2.8,and10.4inthetextbook(8thedition). Theproblemsare: Prob.2.3:Listthemajordisadvantageswiththelayeredapproachtoprotocols. Prob.2.6:InFigure2.2,exactlyoneprotocoldataunit(PDU)inlayerNise
School: Auburn
ELEC 5120/6120 Homework Solution 1 2.3 Perhaps the major disadvantage is the processing and data overhead. There is processing overhead because as many as seven modules (OSI model) are invoked to move data from the application through the communications s
School: Auburn
ELEC 5120/6120 Homework Assignment 9 Question 10.6: What is the significance of packet size in a packet-switching network? Problem 10.2: (a) If a crossbar matrix has n input lines and m output lines, how many crosspoints are required. (b) How many crosspo
School: Auburn
Homework1 NingkaiTang Prob. 2.3: List the major disadvantages with the layered approach to protocols. Answer:1.Protocolstandardsmaybemuchmorecomplexwithmorelayers.Wehaveto makeeveryprotocolsatisfythefunctionofeachlayerandpreciselyservetheupperlayer. So,wh
School: Auburn
ELEC 5120/6120 Homework Assignment 11 Question 13.1: When a node experiences saturation with respect to incoming packets, what general strategy may be used? Question 13.3: Give a brief explanation of each of the congestion control techniques illustrated i
School: Auburn
Homework9 NingkaiTang Question 10.6: What is the significance of packet size in a packet-switching network? Answer: Packetsizemayaffecttheefficiencyofnetwork.Whenseparatepacketinto smallerpiecescanexploitpipelinetechnologybetterforwecantransmitmorepackets
School: Auburn
ELEC 5120/6120 Homework Solution 11 Q13.1 Two general strategies can be adopted. The first such strategy is to discard any incoming packet for which there is no available buffer space. The alternative is for the node that is experiencing these problems to
School: Auburn
ELEC 5120/6120 Homework Assignment 10 Question 12.4: What are the advantages and disadvantages of adaptive routing? Prob. 12.1: Consider a packet switching network of N nodes, connected by the following topologies: (i) Star: once central node with no atta
School: Auburn
Homework10 NingkaiTang Question 12.4: What are the advantages and disadvantages of adaptive routing? Answer:Advantages: 1. Canrecoverfromnodefailure; 2. Candealwithcongestion; 3. Betterperformancebasedonthe2pointsabove. Disadvantages: 1. Additionalworkonc
School: Auburn
ELEC 5120/6120 Homework Solution 10 12.4 Advantages: (1) An adaptive routing strategy can improve performance, as seen by the network user. (2) An adaptive routing strategy can aid in congestion control. Because an adaptive routing strategy tends to balan
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 Digital Logic Circuits Summer 2012 Final Review Solutions Problem 1: What is the output of the following circuit if the delay of each inverter is 1/6 nanosecond? OUTPUT Answer: The output is inverted every ! nanosecond. The circuit will produce
School: Auburn
Course: Microelectronic Fabrication
ELEC 5730/6730 Course Information Notice: This outline may be revised at any time during the term Course Objective: This course is designed to develop an understanding of the fundamentals of integrated circuit (i.e., microelectronic) processing technology
School: Auburn
Name (4 points): A Solution ELEC-3500 Spring 2012 Exam #2 This is a closed book exam, but one 8.5 11-inch sheet of notes and a calculator may be used. Absolutely no wireless services (including cell phones) may be used during the exam. The four problems a
School: Auburn
School: Auburn
Course: Digital Signal Processing
R. Review Materials Contents R1 Mathematical Formulas and Identities R1.1 Finite and Innite Sums of Numbers1 . . . . . R1.2 Power Series . . . . . . . . . . . . . . . . . . . R1.3 Factorial . . . . . . . . . . . . . . . . . . . . . R1.4 Permutations and C
School: Auburn
Course: Analog Electronics
3700 Exam Review II Topics to be covered: NonidealOperationalAmplifiers SmallSignalModelingandLinearAmplification SingleTransistorsAmplifiers Midterm II on 3/30 (Friday). Midterm II covers chap 3, 4, 5. You may bring two sheets of papers (4 pages double s
School: Auburn
Course: Analog Electronics
BJT Small-Signal Model 3700 Exam Review I Topics to be covered: Cbc Introduction and Review for Microelectronic Devices Ideal Operational Amplifiers depend on bias You may want to summarize your review on a couple of sheets (double sided is OK). Bring a c
School: Auburn
School: Auburn
School: Auburn
School: Auburn
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design HW-4 Submitted by Mridula Allani Architectures for Silicon Nanoelectronics and Beyond,Computer, vol. 40, no. 1, pp. 25-33, January 2007. R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Ora
School: Auburn
Course: Special Topics In Electrical Engineering Frequency Synth Ic Dsn
Vector Generation using Spectral Methods Ayoush M Dixit Electrical and Computer Engineering Department Auburn University, Auburn, AL-36849 Email: dixitam@auburn.edu Abstract Two new test generation algorithms for combinational and sequential circuits have
School: Auburn
ELEC 5120/6120: Telecommunication Networks Introduction Mao, Auburn University Communication Networks Problem How to provide connection to a given set of devices that want to exchange information Device: telephone, computer, terminals, etc. Simple Soluti
School: Auburn
Telecommunication Networks Circuit Switching and Packet Switching Mao, Auburn University Switched Network Mao, Auburn University 2 Nodes A collection of nodes and connections is a communications network Nodes may connect to other nodes only, or to stati
School: Auburn
Telecommunication Networks Protocol Architecture, TCP/IP, and Internet-Based Applications Mao, Auburn University Protocol Architecture, TCP/IP, and Internet-Based Applications To destroy communication completely, there must be no rules in common between
School: Auburn
Telecommunication Networks Congestion in Data Networks Mao, Auburn University What Is Congestion? Congestion occurs when the no of packets being transmitted through the network approaches the packet handling capacity of the network Congestion control aim
School: Auburn
Telecommunication Networks Routing in Switched Networks Mao, Auburn University Traditional Circuit Switching Mao, Auburn University 2 Space Division Switch 0 1 A crosspoint Mao, Auburn University 3 Switched Network Mao, Auburn University 4 Routing in
School: Auburn
Telecommunication Networks Data Transmission (a) Mao, Auburn University Data Transmission Mao, Auburn University 2 Transmission Terminology Data transmission occurs between a transmitter & receiver via some medium Guided medium e.g., twisted pair, coaxi
School: Auburn
Telecommunication Networks Multiplexing Mao, Auburn University How to Share a Link Multiplexing Frequency division multiplexing (FDM) Time division multiplexing (TDM) Wavelength division multiplexing (WDM) Code division multiple access (CDMA) Interleave
School: Auburn
Telecommunication Networks Signal Encoding Techniques Mao, Auburn University Signal Encoding Techniques Mao, Auburn University 2 Digital Data, Digital Signal Line coding Digital signal discrete, discontinuous voltage pulses each pulse is a signal elemen
School: Auburn
Telecommunication Networks Random Access From Data Communications and Networking, Behrouz A. Forouzan Mao, Auburn University Multiple Access Mao, Auburn University 2 Random Access ALOHA Carrier Sense Multiple Access Carrier Sense Multiple Access with Co
School: Auburn
Telecommunication Networks Data Transmission (b) Mao, Auburn University Data and Signals Data: analog or digital Signal: analog or digital Represent analog data by Analog signals Digital signals Represent digital data by Digital signals Analog signals M
School: Auburn
Telecommunication Networks Transmission Media Mao, Auburn University Overview Transmission medium and physical layer From Data Communications and Networking, Behrouz A. Forouzan Mao, Auburn University 2 Classes of Transmission Media Characteristics and
School: Auburn
Telecommunication Networks Digital Data Communications Techniques Mao, Auburn University Asynchronous and Synchronous Transmission Timing problems require a mechanism to synchronize the transmitter and receiver receiver samples stream at bit intervals if
School: Auburn
Telecommunication Networks Data Link Control Protocols Mao, Auburn University Data Link Control Protocols The logic layer above the physical layer Requirements and objectives for effective data communication framing and frame synchronization flow control
School: Auburn
Course: Embedded Computing Systems
Operating systems The operating system controls resources: who gets the CPU; when I/O takes place; how much memory is allocated. how processes communicate. The most important resource is the CPU itself. CPU access controlled by the scheduler. Embedded vs.
School: Auburn
Course: Embedded Computing Systems
Embedded Computing Platforms Chapter 4 (Section 4.1) ELEC 5260/6260 Spring 2008 Platform components CPUs. Interconnect buses. Memory. Input/output devices. Implementations: System-on-Chip (SoC) vs. Multi-Chip Microcontroller vs. microprocessor Commercial
School: Auburn
Course: Embedded Computing Systems
Processes and Operating Systems (Text: Chapter 6) Multiple tasks and multiple processes. Preemptive real-time operating systems (RTOS) Scheduling Resource management Interprocess communication Performance Book examples: freeRTOS.org, POSIX/Linux, Windows
School: Auburn
Course: Embedded Computing Systems
Formal System Design Process with UML Use a formal process & tools to facilitate and automate design steps: Requirements Specification System architecture Coding/chip design Testing Text: Chapter 1.3,1.4 Object-Oriented Design Describe system/design as i
School: Auburn
Course: Embedded Computing Systems
Inter-IC Sound (I2S) Bus Optimized for digital audio data transmission 3-line serial bus lines SD: Two time-multiplexed data channels WS: Word Select (0=left channel, 1 = right channel) SCK: Clock Bus master generates SCK and WS Bus master = transmitte
School: Auburn
Course: Embedded Computing Systems
I2C bus (Inter-Integrated Circuit) Designed for low-cost, medium data rate applications. (Phillips Semiconductor, 1980s) Tutorial: http:/www.esacademy.com/faq/i2c/ Characteristics: serial, byte-oriented; multiple-master; fixed-priority arbitration; mo
School: Auburn
Course: Embedded Computing Systems
Serial Peripheral Interface (SPI) Synchronous serial data transfers Multipoint serial communication between a master and a slave device Clock permits faster data rates than async communications (framing unnecessary) Signals = clock, data in/out, slave sel
School: Auburn
Course: Embedded Computing Systems
Analog input subsystem Property being measured input transducer signal conditioning sample & hold analog to digital conv. Digital value to CPU convert property to electrical voltage/current produce convenient voltage/current levels over range of interest
School: Auburn
Course: Embedded Computing Systems
Inter-process communication Chapter 6.4 Interprocess communication Interprocess communication (IPC): OS provides mechanisms so that processes can pass data. Two types of semantics: blocking: sending process waits for response; non-blocking: sending proces
School: Auburn
Course: Embedded Computing Systems
CPUs Chapter 3.5 Caches. Memory management. ARM Cortex-A9 Configurations ARM Cortex A9 Microarchitecture Main System Memory ARM Cortex-A9 MPCore VLSI D&T Seminar - Victor P. Nelson 2/29/2012 Caches and CPUs data cache controller address CPU data cache add
School: Auburn
Course: Embedded Computing Systems
CMSIS Real Time Operating System (Based on Keil RTX) Reference: Keil uVision5 Help Files From the MDK-ARM Version 5 Release Notes CMSIS This version of MDK V5 ships with the CMSIS 3.20 Software Pack. The CMSIS Pack includes CMSIS-RTOS RTX, a CMSIS-RTOS co
School: Auburn
Course: Embedded Computing Systems
Keil ARM Real-Time Library (RL-ARM) Real-Time Executive (RTX) Kernel Reference: Keil Help Files Using RTX in a project Project > Options for Target: Copy RTX_Config.c from \Keil\ARM\Startup for STM32F4xx family Select: Operating System > RTX Kernel Modify
School: Auburn
Course: Embedded Computing Systems
Input/Output Devices Chapter 3: Section 3.1, 3.2 Chapter 3 - CPUs Beyond the instruction set: Input and output. Busy-Wait Interrupt-Driven Supervisor mode, exceptions, traps. Input/output on the STM32F4 microcontroller I/O ports Busy-wait programm
School: Auburn
Course: Embedded Computing Systems
ARM Processor ARM = Advanced RISC Machines, Ltd. ARM licenses IP to other companies (ARM does not fabricate chips) 2005: ARM had 75% of embedded RISC market, with 2.5 billion processors ARM available as microcontrollers, IP cores, etc. www.arm.com Based o
School: Auburn
Course: Embedded Computing Systems
Texas Instruments TMS 32C5x DSP Characteristics of TI C5x DSPs TI C5x DSP CPU Instruction Fetch Data Processing Key DSP Instructions MAC pma,dma multiply/accumulate ACC + P -> ACC pma x dma -> P (repeatable with pma+1) MACD pma,dma -multiply/accumulate
School: Auburn
Course: Embedded Computing Systems
Interrupt-Driven Input/Output Chapter 3: Section 3.2.4 ARM & Cortex-M4 User Manuals Interrupt I/O Busy/wait is very inefficient. CPU cant do other work while testing device. Hard to do simultaneous I/O. Interrupts allow a device to change the flow of
School: Auburn
Course: Embedded Computing Systems
ELEC 5260/6260 Embedded Computing Systems Spring 2014 Victor P. Nelson Text: Computers as Components, 3rd Edition Prof. Marilyn Wolf (Georgia Tech) Course Topics Embedded system design & modeling The embedded computing space. System design methodologie
School: Auburn
Course: Embedded Computing Systems
Example: Model Train Controller Purposes of example: Follow a design through several levels of abstraction. Gain experience with UML. Model train setup rcvr motor power supply console header address command ECC Requirements Console can control 8 trains o
School: Auburn
Course: Embedded Computing Systems
The Embedded System Design Process Wolf Text - Chapter 1.2 Design methodologies A procedure for designing a system. Understanding your methodology helps you ensure you didnt skip anything. Compilers, software engineering tools, computer-aided design (C
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Spring 2014 Advanced VLSI Design Introduction to CAD Tools Murali Dharan 08/01/2014 Course Objectives Learn basic ideas, concepts, theory and methods. Get experience with tools and techniques. VLSI Design Methods Algorithms and architectures Hig
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Technology Mapping Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 14, Apr 25
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Soft Errors and Fault-Tolerant Design Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr1
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770: Advanced VLSI Design Spring 2014 Model-Based and Alternate Tests Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spr
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770: Advanced VLSI Design Spring 2014 Analog and Radio Frequency (RF) Testing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_S
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Linear Programming A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawa
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Zero-Skew Clock Routing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 2014, Mar 19
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 A Linear Programming Solution to Clock Constraint Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagra
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Sprin
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Retiming Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Spring 2014, Fe
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Constraint Graph and Retiming Solution Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Verification Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html Spring 2014
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Timing Verification and Optimization Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr1
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Timing Simulation and STA Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.ht
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 VLSI Yield and Moores Law Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.htm
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Spring 2014 Introduction Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http:/www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 2014, Jan 13 ELE
School: Auburn
Course: Advanced Vlsi Design
Choice of Tests for Logic Veri cation and Equivalence Checking and the Use of Fault Simulation Bell Labs, Lucent Technologies 700 Mountain Avenue, Room 2C-476 Murray Hill, NJ 07974 USA va@research.bell-labs.com Vishwani D. Agrawal A new method is proposed
School: Auburn
Course: Advanced Vlsi Design
Characteristic Polynomial Method for Verification and Test of Combinational Circuits Vishwani D. Agrawal David Lee AT&T Bell Laboratories Murray Hill, NJ 07974 Abstract This paper gives a new and efficient method of determining the equivalence of two give
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #3 Periodic function f(t) = f(t+nT0) T0 period 15 Output Voltage (V) 10 T0 5 0 0 0.01 0.02 0.03 -5 -10 -15 Time (s) 0.04 0.05 Average value Favg Favg 1 T0 T0 f (t )dt o RMS value Frms Frms 1 T0 T0 o f 2 (t )dt Four
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #12 Isolated DC-DC Converters Basic Transformer i1 + v1 - i2 N1 N2 + v2 - Magnetic Equivalent Circuit Rc = lc/ Ac N N N2i2 N1i1 S S Ideal Transformer Assumptions For the windings, Electric fields produced by the
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #8 DC-DC Converters 4 Boost Converter iin = iL L + vL + vD - - + vT Vin iT iD C - iC + v0 - R With the switch closed: iin = iL L + vL - + C Vin v0 R - With the switch open: iin = iL L + vL Vin - + C v0 - R When iL
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #6 DC-DC Converter 2 Switching Power Pole Buck Converter in A 0 Boost Converter With the switch closed: in L L in With the switch open: 0 L L in L L on in 0 s L max L min on s C on 0 s iL Ton Ts t Ts t iD Ton iL To
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #4 DC-DC Converters 1 DC-DC Converters DC Source: Rectifier or Battery DC-DC Converter Load Objective: Maintain a desired DC voltage at the load with variations in the load and the input voltage Applications: Compu
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #17 Rectifiers #4 Controlled Rectifiers + + vT - + v0(t) vs(t) - - R 200 Source and Load Voltage (V) 150 Load Voltage 100 50 0 -50 45 Source Voltage -100 -150 -200 Angle (degrees) 360 150 100 Thyristor Voltage (V)
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #18 AC-AC Converters AC-AC Conversion AC Source Fixed Amplitude and Frequency AC-AC Converter Load Convert fixed amplitude and frequency AC to variable amplitude and frequency AC Some applications: Induction Motor
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #22 Buck Converter L + Vin C v0 - R Continuous Mode With the switch closed: L + iL vL - + C Vin v0 - With the switch open: L + v L iL C + v0 - R R vL, iL vL Vin - V0 iL Ts Ton t -V0 iin, iD iin iD t iT Lr + Vin vC
School: Auburn
Course: Power Electronics
ELEC 5610/6610 Power Electronics Lecture #21 T1 Vin + D1 vT1 iT1 iL = I0 L T2 D2 iT1 Safe Operating Area I0 Vin vT1 Snubber Circuits Turn-on Turn-off D1 IL VS iQ Q + vQ - Switch voltage VS IL Turn off power losses Switch current toff = ts + tf IL D1 VS R
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 4, 2012 Broun 306, 12:00PM2:30PM Total 25 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before tur
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, October 6, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers be
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Final Exam, December 8, 2011 Broun 113, 4:00-6:30PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them i
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 18, 2013 Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Final Exam, May 1, 2013 Total 25 points Problem 1: (3 points) A pipelined MIPS datapath may write a new branch address to the program counter (PC) in the execute cycle in case the branch is taken. This
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Class Test II, October 12, 2011 Broun 113, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: DIGITAL LOGIC CIRCUITS
ELEC 2200-002 Digital Logic Circuits Class Test II, October 22, 2014 Broun 238, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: DIGITAL LOGIC CIRCUITS
ELEC 2200-002 Digital Logic Circuits Class Test I, September 12, 2014 Broun 238, 2:00PM-2:50PM Total 20 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning
School: Auburn
Course: Advanced Vlsi Design
ELEC 7770 Advanced VLSI Design Final Exam, May 2, 2012 Broun 113, 4:00PM6:30PM Total 35 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before turning them in. Thank you
School: Auburn
Course: Advanced Vlsi Design
Name _ ELEC 7770 Advanced VLSI Design Final Exam, May 4, 2007 Broun 235, 5:00PM-7:30PM Total 35 points Instructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure to revise your answers before turning them in. T
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 2, April 11, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, February 10, 2012 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 28, 2011 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 8, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers befo
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 6, 2009 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt any four out of the first five problems. Be sure to revis
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 28, 2011 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 1, March 8, 2010 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers befo
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 6, 2009 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt any four out of the first five problems. Be sure to revis
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 5, 2008 Broun 306, 11:00-11:50AM Total 24 points Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers bef
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, March 5, 2007 Total 24 points Problem 1: 5 points Implement a pseudoinstruction to move data from a memory location whose address is in rsrc register to another memory location whose addre
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 19, 2008 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all four (4) problems. Be sure to revise your answer
School: Auburn
Course: Computer Architecture And Design
Class Test 1, October 16, 2009 Broun 306, 11:00-11:50AM Total 25 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in. Please number your answer shee
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 21, 2007 Total 24 points Instructions: Please read all problems before writing your answers. Attempt all six (6) problems. Be sure to revise your answers before turning them in.
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 24, 2004 Total 24 points Problem 1: 3 points a. Draw a block diagram of the hardware of a computer identifying each block. b. How do the blocks communicate with each other? c. Wh
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, October 5, 2005 (rescheduled October 7, 2005) Total 24 points Problem 1: 6 points a. Assume that a CPU can perform a multiplication in 12ns, an addition in 1ns and a subtraction in 1.5ns.
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test I, September 11, 2006 Total 24 points Problem 1: 8 points a. Assume that a CPU can perform a multiplication in 10ns, an addition in 1ns and a subtraction in 1.5ns. Given that values of a and
School: Auburn
Course: Communication Systems
This image cannot currently be displayed. Example 3.1: Single-tone AM Design factor: modulation factor Mao & Li @ AU 14 This image cannot currently be displayed. Example 3.1 (contd.) Mao & Li @ AU 15 This image cannot currently be displayed. Example 3.1
School: Auburn
Course: Communication Systems
Quantization Noise: Example A full-load sinusoidal m(t) of amplitude Am, average 2 power is: PS Am / 2 Full-load Am=mmax 2 2 Average signal power is: PS Am / 2 mmax / 2 The quantizers output signal-to-noise ratio is: Average signal power (SNR ) O Average
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 (2 pts) Name:_ Test #3: 4/13/11 Part I (25 points): Only a simple instrument of writing is allowed. 1. (5 points) Fill in the following table: Parameter Units Name Time average power density vector P(r, , ) P s m2 Directivity 2. (3 points) How i
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Final Exam Fall 2009 (1 pt) Name:_ Indicate your program: (EE, WIRE, Other): _ (40 pts) Part 1: Simple writing instrument only! 1. (8 pts) Fill in the following grand Maxwells Equation table. Differential form Gausss Law Integral form Gausss Law
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Name:_ Test #3: 11/4/09 Part I (25 points): Only a simple instrument of writing is allowed. 1. (5 points) Fill in the following table: Parameter Units W/m2 P(r, , ) Name Time average power density vector P Dmax Rrad - 2. (2 points) What is the d
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Name:_ Test #2 3/9/11 Part I: Only a simple instrument of writing is allowed. 1. (2 pts)(choose the correct answer) In air-filled rectangular waveguide, the cutoff frequency for the TE10 mode is primarily determined by: (a) the long dimension a
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Final Exam Spring 2011 (1 pt) Name:_ (35 pts) Part 1: Pencil only! 1. (1 pts each) FillinthefollowinggrandMaxwellsEquationtable. Differential form GausssLaw Integral form GausssLaw for Mag. Fields FaradaysLaw AmperesCircuit Law 2. (1 pt each) Fi
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Sample Test #1 Summer 2009 Name:_ Part I: Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. Fill in the following table. Symbol Name (what the symbol represents in Stan
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 (1 pt) Name:_ Test #2 10/5/09 Part I: Only a simple instrument of writing is allowed. 1. (2 pts)(choose the correct answer) In air-filled rectangular waveguide, the cutoff frequency for the TE01 mode is primarily determined by: (a) the metal con
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Test #1 Fall 2009 (1 pt) Name:_ Part I: Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (8 pts) The electric field of a propagating wave is given by: E = 2.5e-0.020y
School: Auburn
Course: Electromagnetics For Wireless Communication
ELEC 3320 Test #1 Name:_ Spring 2011 Part I: Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (5 pts)A material has constitutive properties . At an angular frequency : (a) give
School: Auburn
Course: Electrical
ELEC 3310 Test #3 Name:_ Spring 09, 4/10/09 Part I (4 points each): Closed notes/closed calculator/pencil only 1. Give the formula for the Law of Biot-Savart. Identify the units for each component. 2. Give the formulaforAmperesCircuitLaw.Identifytheunitsf
School: Auburn
Course: Electrical
ELEC 3310 Final Exam Spring 2009 Name:_ Part I (40 points): Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (5points) Fill in the following table. Symbol Name (what the symbol
School: Auburn
Course: Electrical
ELEC 3310 Test #3 (1 point) Name:_ Fall 10, 11/11/10 Part I (4 points each): Closed notes/closed calculator/pencil only 1. What is the formula for the Lorentz force equation? What are the standard units associated with eac h term in this equation? 2.Givet
School: Auburn
Course: Electrical
ELEC 3310 Final Exam Fall 2010 (1 pt) Name:_ Part I (45 points): Closed notes/closed calculator/pencil only. Hint: you will be penalized if you do not represent a vector quantity properly. 1. (8 points) Fill in the following table. Symbol Name (what the s
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Class Test, April 6, 2009 Total 25 points Broun 125, 3:00-3:50PM Problem 1 (6 points): In a CMOS cell library, every two-input combinational gate (inverting, noninverting or exclusive-OR type) co
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Class Test, March 30, 2011 Total 25 points Broun 102, 3:00-3:50PM Problem 1 (5 points): State the requirement on the supply voltage such that the shortcircuit power is completely eliminated. Then
School: Auburn
Course: Low-Power Design Of Electronic Circuits
Name _ ELEC 6270 Low-Power Design of Electronic Circuits Problem 1: 6 points In a CMOS technology, every two input gate (inverting or noninverting or exclusive-OR type) consumes one unit of dynamic power. A flip-flop consumes 8 units of dynamic power only
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Final Exam, May 7, 2009 Total 25 points Broun 125, 4:00-6:30PM Problem 1: 6 points For the power management techniques listed in table below, specify the influence on power and energy as reduced,
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Final Exam, May 4, 2011 Total 25 points Broun 102, 4:00-6:30PM Problem 1: 5 points Using the Elmore delay formula, show that the delay of a long interconnect of length s with distributed resistan
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Class Test, April 5, 2013 Total 25 points Broun 113, 2:00-2:50PM Problem 1 (6 points): A CMOS logic gate has a supply voltage V volts and an output node capacitance C. Write the following express
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Class Test, April 5, 2013 Total 25 points Broun 113, 2:00-2:50PM Problem 1 (6 points): A CMOS logic gate has a supply voltage V volts and an output node capacitance C. Write the following express
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Final Exam, April 29, 2013 Total 25 points Broun 113, 4:00-6:30PM Problem 1: 5 points Using the Elmore delay formula, show that the delay of a long interconnect of length s is proportional to s2.
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Final Exam, April 29, 2013 Total 25 points Broun 113, 4:00-6:30PM Problem 1: 5 points Using the Elmore delay formula, show that the delay of a long interconnect of length s is proportional to s2.
School: Auburn
Course: Computer Architecture And Design
ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 2, April 5, 2013 Instructions: Please read all problems before writing your answers. Attempt all five (5) problems. Be sure to revise your answers before turning them in. Please number your a
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 3 Solution Assigned 9/12/11, due 9/19/11 Problem 1: For 3-bit 2s complement binary integers, construct 4-bit even and odd parity codes by adding a parity bit in the most significant bit position. Ans
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2012 Homework 9 Solution Assigned 4/9/12, due 4/18/12 Problem 1: Run times for three programs are recorded on two processors: Program A B C D Run time (seconds) Processor X Processor Y 1 20 20
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2013) Homework 3 Solution Problem 1: Execution times of hardware blocks of a single cycle datapath are as follows: Multiplexer Control Register file read or write Sign extension Shift left by 2 Adder or ALU Instruction or da
School: Auburn
Ch 2 Homework 1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 2 Solution Assigned 9/2/11, due 9/12/11 Problem 1: Using the method of positive binary integer multiplication, multiply 4-bit 2s complement integers, 1110 1101, to obtain an 8-bit result. Show the st
School: Auburn
Course: Computer Architecture And Design
ELEC 5200-001/6200-001 (Spring 2010) Homework 2 Solution Problem 1: How many IAS instructions require memory data access? List those that do not require memory data access. Not counting pseudoinstructions, list those MIPS instructions that require memory
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Problem 2: For two variables a and b of a Boolean algebra, use the axioms to
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 6 Solution Assigned 10/17/11, due 10/24/10 Problem 1: A house alarm system is designed to sense several conditions represented by binary (0,1) Boolean variables, A, F, M, and W, defined as: A F M W =
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Answer: The minimized function, as shown on the following K
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Problems Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
Course: Low-Power Design Of Electronic Circuits
ELEC 5270-001/6270-001 Low-Power Design of Electronic Circuits Homework 2 Solution Problem 1: A 32 bit bus operates at 1.0V and 2GHz clock rate. Each bit wire, driven by a CMOS buffer, has a total capacitance of 2pF. Each wire has a toggling probability o
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-001 Digital Logic Circuits Fall 2011 Assigned 11/4/11, due 11/11/11 Homework 8 Problem 1: Using Karnaugh map minimize the Boolean function: F(A, B, C, D) = m(2, 3, 6, 7, 11, 12, 13, 15) Problem 2: Sketch a two-level AND-OR gate-level circuit for
School: Auburn
1. Create a zone file for a domain, wareagle.com. This zone contains a. DNS servers: ns1.wareagle.com, ns2.wareagle.com, ns3.wareagle.com b. A web server: www.wareagle.com or wareagle.com c. An email server: mail.wareagle.com d. A FTP server: ftp.ns.warea
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 5 Solution Assigned 10/3/11, due 10/10/11 Problem 1: Prove that the number of elements in a Boolean algebra must be even. Answer: Postulate 6 requires that every element must have a unique complement
School: Auburn
Course: Digital Logic Circuits
ELEC 2200-003 Digital Logic Circuits Fall 2011 Homework 7 Solution Assigned 10/26/10, due 10/31/10 Problem 1: A four-variable Boolean function is expressed as a sum of three product terms (or cubes): F ( A, B, C , D) = ABD + ABC + ACD (a) Using a Karnaugh
School: Auburn
ELEC 5120/6120 Homework Solution 5 With error detection, all odd number of errors can be detected. So after parity check, the remaining (undetected errors) are even-number errors, i.e., 2-, 4-bit errors either in the first byte or in the second byte. P1 =
School: Auburn
Homework5 NingkaiTang Prob. 6.2: A data source produces 7-bit IRA characters. Derive an expression of the maximum effective data rate (rate of IRA data bits) over an x-bps line for the following: (a) Asynchronous transmission, with a 1.5unit stop element
School: Auburn
ELEC 5120/6120 Homework Assignment 5 Problems 6.2, 6.10, 6.13, 6.14(b)(c), and 6.17 in Chapter 6. Prob. 6.2: A data source produces 7-bit IRA characters. Derive an expression of the maximum effective data rate (rate of IRA data bits) over an x-bps line fo
School: Auburn
Homework4 NingkaiTang Prob. 4.3: Given a 100 W power source, what is the maximum allowed length for the following transmission media if a signal of 1 W is to be received? (a) 24-gauge (0.5 mm) twisted pair operating at 300 kHz. (b) 24gauge (0.5 mm) twiste
School: Auburn
ELEC 5120/6120 Homework 4 Homework assignment 4: Problems 4.3, 4.14, 4.15, 5.6, 5.9 and 5.10 in the textbook. The problems are: Prob. 4.3: Given a 100 W power source, what is the maximum allowed length for the following transmission media if a signal of 1
School: Auburn
ELEC 5120/6120 Homework Solution 3 3.21 C = B log2(1 + SNR) 20 106 = 3 106 log2(1 + SNR) log2(1 + SNR) = 6.67 1 + SNR = 102 SNR = 101 3.23 (Eb/N0) = 151 dBW 10 log 2400 10 log 1500 + 228.6 dBW = 12 dBW Source: [FREE98] 4.1 Elapsed time = (5000 km)/(1000 k
School: Auburn
ELEC 5120/6120 Homework 2 Homework assignment 2: Problems 3.13, 3.14, 3.15, 3.16, and 3.19 in the textbook. The problems are: Prob. 3.13 (a) Suppose that a digitized TV picture is to be transmitted from a source that uses a matrix of 480*500 picture elem
School: Auburn
ELEC 5120/6120 Homework 3 Homework assignment 3: Problems 3.21, 3.23, 4.1, 4.2, and 4.17 in the textbook. The problems are: Prob. 3.21: Given a channel with an intended capacity of 20 Mbps, the bandwidth of the channel is 3 MHz. Assuming white thermal noi
School: Auburn
ELEC 5120/6120 Homework Solution 2 3.13 a. (30 pictures/s) (480 500 pixels/picture) = 7.2 106 pixels/s Each pixel can take on one of 32 values and can therefore be represented by 5 bits: R = 7.2 106 pixels/s 5 bits/pixel = 36 Mbps b. We use the formula: C
School: Auburn
Homework3 NingkaiTang Prob. 3.21: Given a channel with an intended capacity of 20 Mbps, the bandwidth of the channel is 3 MHz. Assuming white thermal noise, what signal-to-noise ratio is required to achieve this capacity? Answer:C= 20*1000000=3*1000000* S
School: Auburn
Homework11 NingkaiTang Question 13.1: When a node experiences saturation with respect to incoming packets, what general strategy may be used? Answer:Wehave3generalstrategies. 1. Congestioncontrol:Whichwillallowstreamratetuningduringtransmissionto ensureco
School: Auburn
Homework2 NingkaiTang Prob. 3.13 (a) Suppose that a digitized TV picture is to be transmitted from a source that uses a matrix of480*500 picture elements (pixels), where each pixel can take on one of 32 intensive values. Assume that 30 pictures are sent p
School: Auburn
ELEC 5120/6120 Homework 1 Homeworkassignment1:Problems2.3,2.5,2.6,2.8,and10.4inthetextbook(8thedition). Theproblemsare: Prob.2.3:Listthemajordisadvantageswiththelayeredapproachtoprotocols. Prob.2.6:InFigure2.2,exactlyoneprotocoldataunit(PDU)inlayerNise
School: Auburn
ELEC 5120/6120 Homework Solution 1 2.3 Perhaps the major disadvantage is the processing and data overhead. There is processing overhead because as many as seven modules (OSI model) are invoked to move data from the application through the communications s
School: Auburn
ELEC 5120/6120 Homework Assignment 9 Question 10.6: What is the significance of packet size in a packet-switching network? Problem 10.2: (a) If a crossbar matrix has n input lines and m output lines, how many crosspoints are required. (b) How many crosspo
School: Auburn
Homework1 NingkaiTang Prob. 2.3: List the major disadvantages with the layered approach to protocols. Answer:1.Protocolstandardsmaybemuchmorecomplexwithmorelayers.Wehaveto makeeveryprotocolsatisfythefunctionofeachlayerandpreciselyservetheupperlayer. So,wh
School: Auburn
ELEC 5120/6120 Homework Assignment 11 Question 13.1: When a node experiences saturation with respect to incoming packets, what general strategy may be used? Question 13.3: Give a brief explanation of each of the congestion control techniques illustrated i
School: Auburn
Homework9 NingkaiTang Question 10.6: What is the significance of packet size in a packet-switching network? Answer: Packetsizemayaffecttheefficiencyofnetwork.Whenseparatepacketinto smallerpiecescanexploitpipelinetechnologybetterforwecantransmitmorepackets
School: Auburn
ELEC 5120/6120 Homework Solution 11 Q13.1 Two general strategies can be adopted. The first such strategy is to discard any incoming packet for which there is no available buffer space. The alternative is for the node that is experiencing these problems to
School: Auburn
ELEC 5120/6120 Homework Assignment 10 Question 12.4: What are the advantages and disadvantages of adaptive routing? Prob. 12.1: Consider a packet switching network of N nodes, connected by the following topologies: (i) Star: once central node with no atta
School: Auburn
Homework10 NingkaiTang Question 12.4: What are the advantages and disadvantages of adaptive routing? Answer:Advantages: 1. Canrecoverfromnodefailure; 2. Candealwithcongestion; 3. Betterperformancebasedonthe2pointsabove. Disadvantages: 1. Additionalworkonc
School: Auburn
ELEC 5120/6120 Homework Solution 10 12.4 Advantages: (1) An adaptive routing strategy can improve performance, as seen by the network user. (2) An adaptive routing strategy can aid in congestion control. Because an adaptive routing strategy tends to balan
School: Auburn
ELEC 5120/6120 Homework Solution 8 Problem 1: Problem 2: Problem 3: Problem 4:
School: Auburn
Homework8 NingkaiTang Problem 1: We have a pure ALOHA network with 100 stations. If Tfr=1 us, what is the number of frames/s each station can send to achieve the maximum efficiency Answer:Aswewanttoachievethemaximumefficiency *Numberofframes/s*Numberofsta
School: Auburn
ELEC 5120/6120 Homework Assignment 8 Problem 1: We have a pure ALOHA network with 100 stations. If Tfr=1 us, what is the number of frames/s each station can send to achieve the maximum efficiency? Problem 2: Repeat Additional Prob. 1 for slotted ALOHA. Pr
School: Auburn
Homework7 NingkaiTang Question 8.6: Why is a statistical time division multiplexer more efficient than a synchronous time division multiplexer? Answer:StatisticalTDMisastateorientedmethod.ItisdifferentfromTDMforitwill allocateresourcedependingontheirusage
School: Auburn
Homework6 NingkaiTang Prob. 7.3: A channel has a data rate of 4 kbps and a propagation delay of 20 ms. For what range of frame sizes does stop-and-wait give an efficiency of at least 50%? Answer:Toreach50%,wehavetheequation: Transmissiontime/(Propagationt
School: Auburn
ELEC 5120/6120 Homework Assignment 7 Question 8.6, Problems 8,1, 8.2, 8.7, and 8.8 in Chapter 8 of the textbook. Question 8.6: Why is a statistical time division multiplexer more efficient than a synchronous time division multiplexer? Prob. 8.1: The infor
School: Auburn
ELEC 5120/6120 Homework Assignment 6 Problems 7.3, 7.4, 7.5, 7.7, and 7.10 in Chapter 7 of the textbook. Prob. 7.3: A channel has a data rate of 4 kbps and a propagation delay of 20 ms. For what range of frame sizes does stop-and-wait give an efficiency o
School: Auburn
ELEC 5120/6120 Homework Solution 7 8.6 A statistical time division multiplexer is more efficient than a synchronous time division multiplexer because it allocates time slots dynamically on demand and does not dedicate channel capacity to inactive low spee
School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
* 03/20/12 16:02:22 * PSpice 16.3.0 (June 2009) * ID# 0 * * E:\Eidson's ELEC 2110 Lab Stuff\Lab 9_Problem Solving_First-order Transient Circuits\Problem4.sch * CIRCUIT DESCRIPTION * * Schematics Version 16.3.0 * Tue Mar 20 16:02:18 2012 * Analysis setu
School: Auburn
Course: Electric Circuit Analysis
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School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 6 DC Measurements II R. M. Nelms revised by John Y. Hung July 6, 2011 Abstract The objectives of this laboratory session are: Review Thevenins and Nortons theorems Measure direct current (dc) electrical quantities such as voltage, current, an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 13 Electrical Measurements in AC Circuits Bei Zhang July 1, 2011 Abstract The objectives of this session are to: Expand usage of the DMM within the National Instruments (NI) ELVIS II+ system, as applied to ac measurements. Teach students how
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 14 Analysis of Variable-frequency Networks Using the NI ELVIS II+ System Bei Zhang July 8, 2011 Abstract The objectives of this session are to: Using NI ELVIS II+ system to investigate networks excited with variable-frequency sinusoidal signal
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 11 MultiSim: AC Analysis Suraj Sindia June 14, 2011 Abstract The objectives of this session are: To learn ac steady state circuit calculations Learn to perform ac analysis using MultiSim circuit simulator Contents 1 Preliminaries: Building an
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 12 Problem Solving: Analysis of AC Circuits R. M. Nelms revised by Suraj Sindia July 7, 2011 Abstract The objectives of this session are: Practice solving ac circuits. Learn how to perform complex number calculations in MATLAB. Contents 1 Sol
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 10 PSpice: AC Analysis R. M. Nelms revised by Bei Zhang July 9, 2011 Abstract The objectives of this session are to: Perform ac steady-state circuit calculations Learn PSpice ac analysis Contents 1 Performing an AC Analysis using PSpice 1.1 D
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 9 Problem Solving: First-order Transient Circuits R. M. Nelms revised by Suraj Sindia July 6, 2011 Abstract The objectives of this session are: Learn to solve transient circuits analytically. Learn to plot analytical expressions in MATLAB. L
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 8 Electrical Measurements: First-order Transient Circuits R. M. Nelms revised by John Y. Hung July 18, 2011 Abstract The objectives of this laboratory session are: Learn how to make measurements using an oscilloscope. Learn how to experimenta
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 7 Problem Solving Using Thevenins & Nortons Theorems R. M. Nelms revised by Suraj Sindia July 6, 2011 Abstract The objectives of this session are: Learn how to determine the Thevenin and Norton equivalent circuits for a given circuit. Learn t
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 5 Problem Solving: Mesh & Nodal Analysis R. M. Nelms revised by Suraj Sindia July 6, 2011 Abstract The objectives of this session are: Learn to solve for current through and voltage across any element in a circuit. Learn to use Kirchos voltag
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 4 Introduction to Virtual Instruments: DC Measurements I Suraj Sindia June 30, 2011 Abstract The objectives of this session are: Learn to use virtual instruments to apply stimulus to electric circuits and capture their response. Learn to use
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 3 Introduction to MultiSim: DC Analysis Bei Zhang and Suraj Sindia July 1, 2011 Abstract The objectives of this session are to: Help students become familiar with the basic features of MultiSim, a circuit simulation software tool Provide an i
School: Auburn
Course: Electrical Engineering
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School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 10 PRELAB Your Name Pages of 6 54\ Prelab Questions (10 points) Answer these questions before coming to lab and turn them in when you arrive. You may do your work on separate paper (for example you might want t
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 9 Prelab Page 6 of 6 Prelab Questions (10 points) Answer these questions before coming to lab and turn them in when you arrive. You may do your work on separate paper (for example you might want to do your work o
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 7 PRELAB I Page 4 of 4 Your Name (V) ICA C,WirOS Prelab Questions (10 points) Answer these questions before coming to lab and turn them in when you arrive. You may do your work on separate paper (for example
School: Auburn
Course: Electrical Engineering
ELEC 2010 Laboratory Manual Experiment 1 - Prelab Page 8 of 8 /L9 Your Name c.ittitc 0S Prelab Questions and Quiz (20 points) (Answer these questions in lab and turn them into your instructor before beginning the in-lab procedure. For subsequent weeks,
School: Auburn
School: Auburn
Jordan Ward ELEC 3030 RF Systems Lab Audio Amplifier Pre-Lab September 15, 2011 2. PQ = _ 4. PQ = _ 6. PQ = _ 8. PQ = _ 1. 3. 4. 5. 7. 8.
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040/3050 Lab 5 Matrix Keypad Interface Using Parallel I/O Goals of this lab exercise Control a peripheral device with the MC9S12C32 microcontroller Use parallel I/O ports to control and access a device Implement program-controlled and/or interrup
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC3040/ 3050 Lab Manual Lab 5 Revised 2/09/11 LAB 5: MATRIX KEYPAD INTERFACE USING PARALLEL I/O THE VELLEMAN 16-KEY MATRIX KEYPAD The purpose of this lab is to use the MC9S12C32 (HCS12) microcontroller to control a peripheral device, interfaced through
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC3040/ 3050 Lab Manual Lab 4 Revised 9/7/2011 LAB 4: INTERRUPT PROCESSING IN C INTRODUCTION The previous labs worked with simple input/output (I/O) devices using programcontrolled I/O; the programs continuously monitored each device to determine when t
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040/3050 Lab Manual Lab 3 Revised 9/9/11 LAB 3: SYSTEM ANALYSIS & DEBUGGING WITH OSCILLOSCOPE AND LOGIC ANALYZER INTRODUCTION The purpose of this lab is to continue to gain experience with designing and testing microcontroller-based systems, and to
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040/3050 Lab Manual Lab 2 Revised 8/19/11 LAB 2: Developing and Debugging C Programs in CodeWarrior for the HCS12 Microcontroller The objective of this laboratory session is to become more familiar with the process for creating, executing and debugg
School: Auburn
Course: Electrical Engineering Laboratory IV
ELEC 3040 Electrical System Design Lab ELEC 3050 Embedded System Design Lab Lab Session 1 Project Creation and Debugging The objective of this laboratory session is to become familiar with the process for creating, executing and debugging application prog
School: Auburn
Course: Electric Circuit Analysis
Pspice Tutorial Setup *do not forget to include schematics part during set up process. After installation you will have the compenents seen below. Start Pspice Schematics as seen in the picture. Other compenents will start automaticly as they are needed.
School: Auburn
Course: Electric Circuit Analysis
ELEC 2110 Lab 3 Exericse 1: Vo = 150 V Ix = -1.25 A Exercise 2: Vo = 7.693 V P6V = 6*4.615m = 27.69 mW (supplied) 3. Vo as Vin is varied from 50V to 150V: Ix as I1 is varied from -5A to 5A: 4. Vo (voltage across Rb) as a function of resistance, Rb: X-Trac
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 2 Introduction to PSpice: DC Analysis R. M. Nelms revised by John Y. Hung and Suraj Sindia July 22, 2011 Abstract The objectives of this laboratory session are: Become familiar with the basic features and capabilities of the circuit simulation
School: Auburn
Course: Electric Circuit Analysis
Lab 3 Solutions: Exercise 1 (20 points): Vo = 150V Ix = -1.25A Exercise 2 (20 points): Vo = 7.69V Power supplied by 6V source = VI = 6V(4.615mA) = 27.69 mW Exercise 3 (20 points): DC Sweep of Vo: 180V 160V 140V 120V 50V V( Vout ) 60V 70V 80V 90V 100V 110V
School: Auburn
Course: Electric Circuit Analysis
EXPERIMENT 1 Basic Electrical Measurements R. M. Nelms revision by John Y. Hung June 7, 2011 Abstract The objectives of this laboratory session are: Learn and apply principles of electrical safety Learn to connect basic electrical circuits Learn to use
School: Auburn
Course: Embedded Computing Systems
ELEC5260/6260 - Embedded Computing Systems Spring Term, 2014 Catalog Data: ELEC 5260/6260. EMBEDDED COMPUTING SYSTEMS (3). Pr. ELEC 2220 or COMP 3350. The design of systems containing embedded computers. Microcontroller technology, assembly language and C
School: Auburn
Course: Computer Aided Design Of Digital Circuits
ELEC 5250/6250 COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (Elective for ELEC, ECPE) 2011 Catalog Data: ELEC 5250/6250. COMPUTER-AIDED DESIGN OF DIGITAL LOGIC CIRCUITS (3) LEC. 3. Pr., ELEC 2220 or COMP 3350. Computer-automated design of digital logic
School: Auburn
Course: Electrical Engineering Laboratory IV
COURSE SYLLABUS ELEC 3040 ELECTRICAL SYSTEM DESIGN LABORATORY ELEC 3050 EMBEDDED SYSTEM DESIGN LABORATORY FALL SEMESTER, 2011 INSTRUCTORS: Victor P. Nelson, Office: Broun 326, Email: nelsovp@auburn.edu John Y. Hung, Office: Broun 227, Email: hungjoh@aubur
School: Auburn
Course: Digital Logic Circuits
ELEC 2200 - DIGITAL LOGIC CIRCUITS SUMMER SEMESTER - 2011 2011 Catalog Data: ELEC 2200. DIGITAL LOGIC CIRCUITS (3). Prereq. COMP 1200 or COMP 1210. Electronic devices and digital circuits; binary numbers; Boolean algebra and switching functions; gates and
School: Auburn
Course: Computer Systems
ELEC 2220 - COMPUTER SYSTEMS Summer 2010 2010 Catalog Data: ELEC 2220. COMPUTER SYSTEMS (3) LEC, 3. Pr., ELEC 2210 or ELEC 2200. Computer hardware and software organization, processor programming models, data representation, assembly language programming,