Lecture 13: Asynchronous Design Example
Design Procedure:
1. Derive a primitive flow table.
2. Remove redundant states.
3. Merge rows.
4. Find a state assignment that avoids races.
5. Complete the output values to avoid hazards.
6. If latches are not used
CE-420 Advanced Logic Systems
Homework 2 Questions
Analysis of Asynchronous Sequential Networks, Races,
and Cycles
Problem 1) Construct a flow table and an output table for the following
circuit.
Problem 2) Construct a flow table and an output table for t
CE-410 Advanced Logic Systems
Lab 3
Asynchronous Logic Analysis
Due Date: 5th Thursday, May 6
Concepts:
Analyzing an asynchronous sequential circuit
Using Xilinx ISE to simulate digital circuits
Objectives:
Analyze an asynchronous sequential circuit
D
CE-410 Advanced Logic Systems
Lab 4
Asynchronous Logic Design
Due Date: 6th Thursday, May 13
Concepts:
Implementing asynchronous Boolean logic
Using the asynchronous sequential logic design flow using one-hot
state assignment
Using Xilinx ISE to simula
Lecture 4: Asynchronous Sequential Networks
No clock signal
Sequential behavior achieved by using feedback into combinational circuit and
reaching a stable state
Next state is reached as soon as the gates can switch, it will not wait to move to
the next
CE-410 Advanced Logic Systems
Homework 9 Questions
Fuzzy Logic Systems
Problem 1)
Hovering over a fixed spot on the ground is a very difficult task
for a helicopter pilot. For this problem, lets consider just one
dimension. A pilot moves forwards and back
CE-410 Advanced Logic Systems
Homework 1 Questions
Review of Boolean Combinational and Sequential Logic
Problem 1) Use the Distributive Law to convert the following SOP equations
to POS equations.
a) Z = A B C E
b) Z = A B B D E
c) Z = A B C D E F
d) Z =
Lecture 5: Asynchronous Sequential Networks
Sequential Circuits without flip-flops
Each discrete gate has a propagation delay the output changes some amount
of time after the input changes
All the propagation delays for a circuit can be grouped up and r
CE-410 Advanced Logic Systems
Homework 8 Solutions
Fuzzy Logic
Problem 1)
Countless correct answers, as long as some common sense
comes into play. This question should demonstrate that context of a
specific problem is extremely important. Below is one pos
CE-410 Advanced Logic Systems
Homework 8 Questions
Fuzzy Logic
Problem 1)
Draw fuzzy membership functions IsVeryShort, IsShort, IsMedium,
IsTall, IsVeryTall given the following contexts:
a) Height of a 10-year old person
b) Height of a full-grown adult ma
CE-410 Advanced Logic Systems
Homework 9 Solutions
Fuzzy Logic Systems
Problem 1) There are many possible, correct answers.
Part a)
Far_behind
Near_behind
Distance
Over
Near_ahead
Far_ahead
1.0
0.5
0.0
-10
-7.5
-5
-2.5
0
2.5
5
7.5
10
Part b)
Back_fast
Bac
CE-410 Advanced Logic Systems
Homework 5 Questions
Hazards
Problem 1) For each of the circuits below, determine the static 1-hazards,
static-0 hazards, and dynamic hazards, if any.
a)
A
C
F
A
B
b)
A
C
D
Z
A
B
C
Problem 2) For the flow tables below, determ
CE-410 Advanced Logic Systems
Homework 1 Solutions
Review of Boolean Combinational and Sequential
Logic
Problem 1)
a) (A C) (A E) (B C) (B E)
b) (A B) (A D) (A E) B (B D) (B E)
c) (A D) (A E) (A F) (B D) (B E) (B F) (C
D) (C E) (C F)
d) (A C E) (A D E) (
CE-410 Advanced Logic Systems
Homework 5 Solutions
Hazards
Problem 1)
a) Static 1 hazard between ABC and ABC.
No static 0 or dynamic hazards.
b) Static 0 hazard between ABCD and ABCD
Dynamic hazard with A.
No static 1 hazards.
Problem 2)
a)
state a, X1X0=
CE-410 Advanced Logic Systems
Homework 7 Solutions
I/O and PLC Functions
Problem 1)
a) 17.4316V, 7.92V
b) 8 mA, 14.6mA
c) 6.648mA, 14.097mA
Problem 2)
a) 645C to 655C, 642.4C to 657.6C, 640.5C to 659.5C, 643.5C to
656.5C
b) 1.48m to 1.52m, 1.41m to 1.59m,
CE-410 Advanced Logic Systems
Homework 7 Questions
I/O and PLC Functions
Problem 1)
a) For a sensor that measures temperature from -190C to 760C
and outputs 0 to 24V, what voltage corresponds to a
temperature of 500C? To 132.5C?
b) For a sensor that measu
Lecture 12: Design of Hazard Free Networks
There is a theorem which allows us to design a circuit that is free from static 1,
static 0, and dynamic hazards.
Theorem:
If the 1-terms of Ft satisfy the following conditions, the network will not contain
stati
CE-410 Advanced Logic Systems
Lab 5
Asynchronous Logic Design
Due Date: 7th Thursday, May 20
Concepts:
Implementing asynchronous Boolean logic without static or dynamic
hazards
Using the asynchronous sequential logic design flow
Using Xilinx ISE to simula
Lecture 11: Hazards
Hazards:
Timing problems due to the time it takes for signals to propagate through wires
and for gates to change their output.
Hazards are caused by different paths to the output having different propagation
times.
Types of Hazards:
CE-410 Advanced Logic Systems
Homework 4 Questions
State Assignments and Output Tables
Problem 1)
Make a proper assignment of internal state variables for each of the
following flow tables by adding a fourth state.
Problem 2)
Make two proper assignments o
Lecture 14: Ladder Logic
Ladder Logic can be described as a combination of the following three things:
Circuits One of the main concepts behind ladder logic is emulating
contact/relay control circuits. That is, providing an electrical path from power to
Lecture 18: Ladder Logic Functions
Data Types
DINT
Signed 32 bit
AI, AQ, R, W (takes 2 addresses)
INT
Signed 16 bit
Any
REAL
Signed floating point 32
bit
AI, AQ, R, W (takes 2 addresses)
UINT
Unsigned 16 bit
Any
BYTE
8-bit string
Any
WORD
16-bit string
An
CE-410 Advanced Logic Systems
Homework 6 Solutions
Ladder Logic
Problem 1)
a)
b)
Homework 6 Solutions
Page 1
CE-410 Advanced Logic Systems
c)
d)
Homework 6 Solutions
Page 2
CE-410 Advanced Logic Systems
Problem 2)
a)
b)
Homework 6 Solutions
Page 3
CE-410
Lecture 16: Overview of PLCs
Programmable Logic Controller
Very robust, reliable computer designed specifically for control
Manufacturing equipment, building heating and cooling, security systems,
naval vessels, aircraft
Vary in size from very small de
Lecture 10: One-Hot State Assignment
Advantages of state assignment methods so far:
Small, efficient logic implementation
Disadvantages of state assignment methods so far:
Structured methods, but still a little guess and test involved.
Variable number
Lecture 19: Ladder Logic Examples
Sequence using discrete components.
1
Lecture 19: Ladder Logic Examples
Sequencer using discrete components.
Basically a one-hot approach.
One stateX variable is true, all others false.
The Next state rung holds a vari