Top Course Tags
A Few Big Assignments
Background Knowledge Expected
Not too easy. Not too difficult.
it is one of the prerequisites for the next verification and synthesis course that is available in USC which is 577b. The professor keeps you busy through out the semester with homeworks and Labs that are done using cadence, Hspice and Perl.
you learn a lot about Physical Design, Logical Effort, SRAM memories and Power Optimization all of which are very crucial in the industry
Hours per week:
Advice for students:
Start your labs and home works early to learn more and take as much help as possible from TAs and the Professor